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REJ09B0241-0100
16
H8S/2144B,H8S/2134B
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series H8S/2144B HD64F2144B H8S/2134B HD64F2134B
Rev.1.00 Revision Date: Jun.24, 2005
Rev. 1.00 Jun.24, 2005 Page ii of xxxii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 1.00 Jun.24, 2005 Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 1.00 Jun.24, 2005 Page iv of xxxii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 1.00 Jun.24, 2005 Page v of xxxii
Preface
The H8S/2144B and H8S/2134B are microcomputers (MCUs) made up of the H8S/2000 CPU employing Renesas Technology's original architecture as their cores, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the H8S/2144B or H8S/2134B in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2144B and H8S/2134B to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 19, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a active-low signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
Rev. 1.00 Jun.24, 2005 Page vi of xxxii
H8S/2144B, H8S/2134B manuals:
Manual Title H8S/2144B, H8S/2134B Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual ADE No. This manual REJ09B0139
User's manuals for development tools:
Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial ADE No. REJ10B0058 ADE-702-282 REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual REJ10B0026
Rev. 1.00 Jun.24, 2005 Page vii of xxxii
Contents
Section 1 Overview ................................................................................................. 1
1.1 1.2 1.3 Features.................................................................................................................................. 1 Block Diagram....................................................................................................................... 3 Pin Arrangements and Functions ........................................................................................... 5 1.3.1 Pin Arrangements ..................................................................................................... 5 1.3.2 Pin Functions in Each Operating Mode .................................................................... 7 1.3.3 Pin Functions .......................................................................................................... 14
Section 2 CPU ....................................................................................................... 19
2.1 Features................................................................................................................................ 19 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 20 2.1.2 Differences from H8/300 CPU ............................................................................... 20 2.1.3 Differences from H8/300H CPU ............................................................................ 21 CPU Operating Modes......................................................................................................... 22 2.2.1 Normal Mode.......................................................................................................... 22 2.2.2 Advanced Mode...................................................................................................... 24 Address Space...................................................................................................................... 26 Register Configuration......................................................................................................... 27 2.4.1 General Registers.................................................................................................... 28 2.4.2 Program Counter (PC) ............................................................................................ 29 2.4.3 Extended Control Register (EXR) .......................................................................... 29 2.4.4 Condition-Code Register (CCR)............................................................................. 29 2.4.5 Initial Register Values ............................................................................................ 31 Data Formats........................................................................................................................ 31 2.5.1 General Register Data Formats............................................................................... 31 2.5.2 Memory Data Formats ............................................................................................ 34 Instruction Set ...................................................................................................................... 35 2.6.1 Table of Instructions Classified by Function .......................................................... 36 2.6.2 Basic Instruction Formats ....................................................................................... 46 Addressing Modes and Effective Address Calculation........................................................ 47 2.7.1 Register Direct--Rn ............................................................................................... 48 2.7.2 Register Indirect--@ERn....................................................................................... 48 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)................. 48 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn..... 48 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32....................................... 49 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32.................................................................... 50
2.2
2.3 2.4
2.5
2.6
2.7
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2.8 2.9
2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC)....................................... 50 2.7.8 Memory Indirect--@@aa:8 ................................................................................... 50 2.7.9 Effective Address Calculation ................................................................................ 52 Processing States.................................................................................................................. 54 Usage Notes ......................................................................................................................... 56 2.9.1 Note on TAS Instruction Usage .............................................................................. 56 2.9.2 Note on STM/LDM Instruction Usage ................................................................... 56 2.9.3 Note on Bit Manipulation Instructions.................................................................... 56 2.9.4 EEPMOV Instruction.............................................................................................. 58
Section 3 MCU Operating Modes .........................................................................59
3.1 3.2 MCU Operating Mode Selection ......................................................................................... 59 Register Descriptions ........................................................................................................... 59 3.2.1 Mode Control Register (MDCR) ............................................................................ 60 3.2.2 System Control Register (SYSCR) ......................................................................... 61 3.2.3 Serial Timer Control Register (STCR) ................................................................... 63 Operating Mode Descriptions .............................................................................................. 65 3.3.1 Mode 1 .................................................................................................................... 65 3.3.2 Mode 2 .................................................................................................................... 65 3.3.3 Mode 3 .................................................................................................................... 65 3.3.4 Pin Functions in Each Operating Mode .................................................................. 65 Address Map in Each Operating Mode................................................................................ 67
3.3
3.4
Section 4 Exception Handling ...............................................................................69
4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 69 Exception Sources and Exception Vector Table .................................................................. 70 Reset .................................................................................................................................... 71 4.3.1 Reset Exception Handling....................................................................................... 71 4.3.2 Interrupts after Reset............................................................................................... 72 4.3.3 On-Chip Peripheral Modules after Reset is Released ............................................. 72 Interrupt Exception Handling............................................................................................... 73 Trap Instruction Exception Handling................................................................................... 73 Stack Status after Exception Handling................................................................................. 74 Usage Note........................................................................................................................... 75
4.4 4.5 4.6 4.7
Section 5 Interrupt Controller ................................................................................77
5.1 5.2 5.3 Features................................................................................................................................ 77 Input/Output Pins ................................................................................................................. 79 Register Descriptions ........................................................................................................... 79 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) .............................................. 80
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5.4
5.5 5.6
5.7
5.8
5.3.2 Address Break Control Register (ABRKCR) ......................................................... 81 5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 81 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)...................................................... 82 5.3.5 IRQ Enable Register (IER) ..................................................................................... 83 5.3.6 IRQ Status Register (ISR)....................................................................................... 84 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) ........................ 85 Interrupt Sources.................................................................................................................. 87 5.4.1 External Interrupts .................................................................................................. 87 5.4.2 Internal Interrupts ................................................................................................... 89 Interrupt Exception Handling Vector Table......................................................................... 89 Interrupt Control Modes and Interrupt Operation ................................................................ 92 5.6.1 Interrupt Control Mode 0........................................................................................ 92 5.6.2 Interrupt Control Mode 1........................................................................................ 95 5.6.3 Interrupt Exception Handling Sequence ................................................................. 98 5.6.4 Interrupt Response Times ..................................................................................... 100 Address Break.................................................................................................................... 101 5.7.1 Features................................................................................................................. 101 5.7.2 Block Diagram...................................................................................................... 101 5.7.3 Operation .............................................................................................................. 101 5.7.4 Usage Notes .......................................................................................................... 102 Usage Notes ....................................................................................................................... 104 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 104 5.8.2 Instructions that Disable Interrupts....................................................................... 105 5.8.3 Interrupts during Execution of EEPMOV Instruction .......................................... 105 5.8.4 IRQ Status Register (ISR)..................................................................................... 105
Section 6 Bus Controller (BSC) .......................................................................... 107
6.1 6.2 6.3 Features.............................................................................................................................. 107 Input/Output Pins............................................................................................................... 108 Register Descriptions......................................................................................................... 109 6.3.1 Bus Control Register (BCR) ................................................................................. 109 6.3.2 Wait State Control Register (WSCR) ................................................................... 110 Bus Control........................................................................................................................ 112 6.4.1 Bus Specifications ................................................................................................ 112 6.4.2 Advanced Mode.................................................................................................... 113 6.4.3 Normal Mode........................................................................................................ 114 6.4.4 I/O Select Signals ................................................................................................. 114 Basic Bus Interface ............................................................................................................ 116 6.5.1 Data Size and Data Alignment.............................................................................. 116 6.5.2 Valid Strobes ........................................................................................................ 117
6.4
6.5
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6.6
6.7
6.5.3 Basic Operation Timing........................................................................................ 119 6.5.4 Wait Control ......................................................................................................... 127 Burst ROM Interface.......................................................................................................... 129 6.6.1 Basic Operation Timing........................................................................................ 129 6.6.2 Wait Control ......................................................................................................... 130 Idle Cycle........................................................................................................................... 131
Section 7 I/O Ports ...............................................................................................133
7.1 7.2 Overview............................................................................................................................ 133 Port 1.................................................................................................................................. 140 7.2.1 Port 1 Data Direction Register (P1DDR).............................................................. 140 7.2.2 Port 1 Data Register (P1DR)................................................................................. 141 7.2.3 Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 141 7.2.4 Pin Functions ........................................................................................................ 142 7.2.5 Port 1 Input Pull-Up MOS .................................................................................... 142 Port 2.................................................................................................................................. 143 7.3.1 Port 2 Data Direction Register (P2DDR).............................................................. 143 7.3.2 Port 2 Data Register (P2DR)................................................................................. 144 7.3.3 Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 144 7.3.4 Pin Functions ........................................................................................................ 145 7.3.5 Port 2 Input Pull-Up MOS .................................................................................... 145 Port 3.................................................................................................................................. 147 7.4.1 Port 3 Data Direction Register (P3DDR).............................................................. 147 7.4.2 Port 3 Data Register (P3DR)................................................................................. 147 7.4.3 Port 3 Pull-Up MOS Control Register (P3PCR)................................................... 148 7.4.4 Pin Functions ........................................................................................................ 148 7.4.5 Port 3 Input Pull-Up MOS .................................................................................... 148 Port 4.................................................................................................................................. 150 7.5.1 Port 4 Data Direction Register (P4DDR).............................................................. 150 7.5.2 Port 4 Data Register (P4DR)................................................................................. 150 7.5.3 Pin Functions ........................................................................................................ 151 Port 5.................................................................................................................................. 154 7.6.1 Port 5 Data Direction Register (P5DDR).............................................................. 154 7.6.2 Port 5 Data Register (P5DR) P3PCR.................................................................... 154 7.6.3 Pin Functions ........................................................................................................ 155 Port 6.................................................................................................................................. 156 7.7.1 Port 6 Data Direction Register (P6DDR).............................................................. 156 7.7.2 Port 6 Data Register (P6DR)................................................................................. 157 7.7.3 Port 6 Pull-Up MOS Control Register (KMPCR)................................................. 157 7.7.4 System Control Register 2 (SYSCR2) .................................................................. 158
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7.3
7.4
7.5
7.6
7.7
7.7.5 Pin Functions ........................................................................................................ 159 7.7.6 Port 6 Input Pull-Up MOS .................................................................................... 161 7.8 Port 7.................................................................................................................................. 162 7.8.1 Port 7 Input Data Register (P7PIN) ...................................................................... 162 7.8.2 Pin Functions ........................................................................................................ 162 7.9 Port 8.................................................................................................................................. 164 7.9.1 Port 8 Data Direction Register (P8DDR).............................................................. 164 7.9.2 Port 8 Data Register (P8DR) ................................................................................ 165 7.9.3 Pin Functions ........................................................................................................ 165 7.10 Port 9.................................................................................................................................. 167 7.10.1 Port 9 Data Direction Register (P9DDR).............................................................. 168 7.10.2 Port 9 Data Register (P9DR) ................................................................................ 169 7.10.3 Pin Functions ........................................................................................................ 169 7.11 Port A (Only for H8S/2144B)............................................................................................ 172 7.11.1 Port A Data Direction Register (PADDR)............................................................ 172 7.11.2 Port A Output Data Register (PAODR)................................................................ 173 7.11.3 Port A Input Data Register (PAPIN) .................................................................... 173 7.11.4 Pin Functions ........................................................................................................ 174 7.11.5 Port A Input Pull-Up MOS ................................................................................... 178 7.12 Port B (Only for H8S/2144B) ............................................................................................ 179 7.12.1 Port B Data Direction Register (PBDDR) ............................................................ 179 7.12.2 Port B Output Data Register (PBODR) ................................................................ 180 7.12.3 Port B Input Data Register (PBPIN)..................................................................... 180 7.12.4 Pin Functions ........................................................................................................ 181 7.12.5 Port B Input Pull-Up MOS ................................................................................... 181
Section 8 14-Bit PWM Timer (PWMX) ............................................................. 183
8.1 8.2 8.3 Features.............................................................................................................................. 183 Input/Output Pins............................................................................................................... 184 Register Descriptions......................................................................................................... 184 8.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL)....................................... 184 8.3.2 PWM (D/A) Data Registers A and B (DADRA, DADRB) .................................. 186 8.3.3 PWM (D/A) Control Register (DACR) ................................................................ 188 Bus Master Interface.......................................................................................................... 189 Operation ........................................................................................................................... 190 Usage Note......................................................................................................................... 196 8.6.1 Module Stop Mode Setting ................................................................................... 196
8.4 8.5 8.6
Section 9 16-Bit Free-Running Timer (FRT)...................................................... 197
9.1 Features.............................................................................................................................. 197
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9.2 9.3
9.4 9.5
9.6 9.7
Input/Output Pins ............................................................................................................... 199 Register Descriptions ......................................................................................................... 199 9.3.1 Free-Running Counter (FRC) ............................................................................... 200 9.3.2 Output Compare Registers A and B (OCRA, OCRB) .......................................... 200 9.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................. 200 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ................................ 201 9.3.5 Output Compare Register DM (OCRDM)............................................................ 201 9.3.6 Timer Interrupt Enable Register (TIER) ............................................................... 202 9.3.7 Timer Control/Status Register (TCSR)................................................................. 203 9.3.8 Timer Control Register (TCR).............................................................................. 206 9.3.9 Timer Output Compare Control Register (TOCR) ............................................... 207 Operation ........................................................................................................................... 209 9.4.1 Pulse Output.......................................................................................................... 209 Operation Timing............................................................................................................... 209 9.5.1 FRC Increment Timing ......................................................................................... 209 9.5.2 Output Compare Output Timing ........................................................................... 210 9.5.3 FRC Clear Timing ................................................................................................ 211 9.5.4 Input Capture Input Timing .................................................................................. 211 9.5.5 Buffered Input Capture Input Timing ................................................................... 212 9.5.6 Timing of Input Capture Flag (ICF) Setting ......................................................... 214 9.5.7 Timing of Output Compare Flag (OCF) setting.................................................... 215 9.5.8 Timing of FRC Overflow Flag Setting ................................................................. 216 9.5.9 Automatic Addition Timing.................................................................................. 217 9.5.10 Mask Signal Generation Timing ........................................................................... 218 Interrupt Sources................................................................................................................ 219 Usage Notes ....................................................................................................................... 220 9.7.1 Conflict between FRC Write and Clear ................................................................ 220 9.7.2 Conflict between FRC Write and Increment......................................................... 221 9.7.3 Conflict between OCR Write and Compare-Match .............................................. 221 9.7.4 Switching of Internal Clock and FRC Operation .................................................. 224 9.7.5 Module Stop Mode Setting ................................................................................... 225
Section 10 8-Bit Timer (TMR) ............................................................................227
10.1 Features.............................................................................................................................. 227 10.2 Input/Output Pins ............................................................................................................... 230 10.3 Register Descriptions ......................................................................................................... 230 10.3.1 Timer Counter (TCNT)......................................................................................... 231 10.3.2 Time Constant Register A (TCORA).................................................................... 231 10.3.3 Time Constant Register B (TCORB) .................................................................... 231 10.3.4 Timer Control Register (TCR).............................................................................. 232
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10.4 10.5
10.6
10.7 10.8
10.3.5 Timer Control/Status Register (TCSR)................................................................. 235 10.3.6 Timer Input Select Register (TISR)...................................................................... 240 Operation ........................................................................................................................... 240 10.4.1 Pulse Output ......................................................................................................... 240 Operation Timing............................................................................................................... 242 10.5.1 TCNT Count Timing ............................................................................................ 242 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 243 10.5.3 Timing of Timer Output at Compare-Match......................................................... 243 10.5.4 Timing of Counter Clear at Compare-Match........................................................ 244 10.5.5 TCNT External Reset Timing............................................................................... 244 10.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 245 Operation with Cascaded Connection................................................................................ 246 10.6.1 16-Bit Count Mode ............................................................................................... 246 10.6.2 Compare-Match Count Mode ............................................................................... 247 Interrupt Sources................................................................................................................ 248 Usage Notes ....................................................................................................................... 249 10.8.1 Conflict between TCNT Write and Clear ............................................................. 249 10.8.2 Conflict between TCNT Write and Increment...................................................... 250 10.8.3 Conflict between TCOR Write and Compare-Match............................................ 251 10.8.4 Conflict between Compare-Matches A and B ...................................................... 252 10.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 252 10.8.6 Mode Setting with Cascaded Connection ............................................................. 254 10.8.7 Module Stop Mode Setting ................................................................................... 255
Section 11 Watchdog Timer (WDT) ................................................................... 257
11.1 Features.............................................................................................................................. 257 11.2 Input/Output Pins............................................................................................................... 259 11.3 Register Descriptions......................................................................................................... 259 11.3.1 Timer Counter (TCNT)......................................................................................... 259 11.3.2 Timer Control/Status Register (TCSR)................................................................. 260 11.4 Operation ........................................................................................................................... 264 11.4.1 Watchdog Timer Mode......................................................................................... 264 11.4.2 Interval Timer Mode............................................................................................. 266 11.4.3 RESO Signal Output Timing (Available for H8S/2144B).................................... 267 11.5 Interrupt Sources................................................................................................................ 267 11.6 Usage Notes ....................................................................................................................... 268 11.6.1 Notes on Register Access ..................................................................................... 268 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 269 11.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 269 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 269
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11.6.5 System Reset by RESO Signal (Available for H8S/2144B) ................................. 270 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................. 270
Section 12 Serial Communication Interface (SCI and IrDA) ..............................271
12.1 Features.............................................................................................................................. 271 12.2 Input/Output Pins ............................................................................................................... 273 12.3 Register Descriptions ......................................................................................................... 273 12.3.1 Receive Shift Register (RSR) ............................................................................... 274 12.3.2 Receive Data Register (RDR) ............................................................................... 274 12.3.3 Transmit Data Register (TDR).............................................................................. 274 12.3.4 Transmit Shift Register (TSR) .............................................................................. 274 12.3.5 Serial Mode Register (SMR) ................................................................................ 275 12.3.6 Serial Control Register (SCR) .............................................................................. 277 12.3.7 Serial Status Register (SSR) ................................................................................. 279 12.3.8 Serial Interface Mode Register (SCMR)............................................................... 281 12.3.9 Bit Rate Register (BRR) ....................................................................................... 282 12.3.10 Keyboard Comparator Control Register (KBCOMP)........................................... 289 12.4 Operation in Asynchronous Mode ..................................................................................... 290 12.4.1 Data Transfer Format............................................................................................ 290 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................. 292 12.4.3 Clock..................................................................................................................... 293 12.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 294 12.4.5 Data Transmission (Asynchronous Mode)............................................................ 295 12.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 297 12.5 Multiprocessor Communication Function.......................................................................... 301 12.5.1 Multiprocessor Serial Data Transmission ............................................................. 303 12.5.2 Multiprocessor Serial Data Reception .................................................................. 305 12.6 Operation in Clock Synchronous Mode............................................................................. 308 12.6.1 Clock..................................................................................................................... 308 12.6.2 SCI Initialization (Clock Synchronous Mode)...................................................... 309 12.6.3 Serial Data Transmission (Clock Synchronous Mode) ......................................... 310 12.6.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 313 12.6.5 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) .................................................................................. 316 12.7 IrDA Operation .................................................................................................................. 318 12.8 Interrupt Sources................................................................................................................ 321 12.9 Usage Notes ....................................................................................................................... 322 12.9.1 Module Stop Mode Setting ................................................................................... 322
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12.9.2 Break Detection and Processing ........................................................................... 322 12.9.3 Mark State and Break Detection ........................................................................... 322 12.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ......................................................................... 322 12.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 322 12.9.6 SCI Operations during Mode Transitions ............................................................. 323 12.9.7 Notes on Switching from SCK Pins to Port Pins .................................................. 327
Section 13 D/A Converter ................................................................................... 329
13.1 Features.............................................................................................................................. 329 13.2 Input/Output Pins............................................................................................................... 330 13.3 Register Descriptions......................................................................................................... 330 13.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 330 13.3.2 D/A Control Register (DACR) ............................................................................. 331 13.4 Operation ........................................................................................................................... 332 13.5 Usage Note......................................................................................................................... 333 13.5.1 Module Stop Mode Setting ................................................................................... 333
Section 14 A/D Converter ................................................................................... 335
14.1 Features.............................................................................................................................. 335 14.2 Input/Output Pins............................................................................................................... 337 14.3 Register Descriptions......................................................................................................... 338 14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 338 14.3.2 A/D Control/Status Register (ADCSR) ................................................................ 339 14.3.3 A/D Control Register (ADCR) ............................................................................. 341 14.3.4 Keyboard Comparator Control Register (KBCOMP)........................................... 342 14.4 Operation ........................................................................................................................... 343 14.4.1 Single Mode.......................................................................................................... 343 14.4.2 Scan Mode ............................................................................................................ 343 14.4.3 Input Sampling and A/D Conversion Time .......................................................... 345 14.4.4 External Trigger Input Timing.............................................................................. 346 14.5 Interrupt Sources................................................................................................................ 347 14.6 A/D Conversion Accuracy Definitions .............................................................................. 347 14.7 Usage Notes ....................................................................................................................... 349 14.7.1 Permissible Signal Source Impedance .................................................................. 349 14.7.2 Influences on Absolute Accuracy ......................................................................... 349 14.7.3 Setting Range of Analog Power Supply and Other Pins....................................... 350 14.7.4 Notes on Board Design ......................................................................................... 350 14.7.5 Notes on Noise Countermeasures ......................................................................... 351 14.7.6 Module Stop Mode Setting ................................................................................... 352
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Section 15 RAM ..................................................................................................353 Section 16 ROM ..................................................................................................355
16.1 Features.............................................................................................................................. 355 16.2 Mode Transitions ............................................................................................................... 357 16.3 Block Configuration........................................................................................................... 360 16.3.1 Block Configuration ............................................................................................. 360 16.4 Input/Output Pins ............................................................................................................... 361 16.5 Register Descriptions ......................................................................................................... 361 16.5.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 362 16.5.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 363 16.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) ..................................................... 364 16.6 Operating Modes................................................................................................................ 365 16.7 On-Board Programming Modes......................................................................................... 366 16.7.1 Boot Mode ............................................................................................................ 366 16.7.2 User Program Mode.............................................................................................. 370 16.8 Flash Memory Programming/Erasing ................................................................................ 371 16.8.1 Programming/Programming-Verifying................................................................. 371 16.8.2 Erasing/Erasing-Verifying .................................................................................... 374 16.9 Programming/Eraseing Protection ..................................................................................... 376 16.9.1 Hardware Protection ............................................................................................. 376 16.9.2 Software Protection............................................................................................... 376 16.9.3 Error Protection..................................................................................................... 376 16.10 Interrupts during Flash Memory Programming/Erasing .................................................... 377 16.11 Programmer Mode ............................................................................................................. 378 16.12 Usage Notes ....................................................................................................................... 378
Section 17 Clock Pulse Generator .......................................................................381
17.1 Oscillator............................................................................................................................ 382 17.1.1 Connecting Crystal Resonator .............................................................................. 382 17.1.2 External Clock Input Method................................................................................ 383 17.2 Duty Correction Circuit ..................................................................................................... 386 17.3 Medium-Speed Clock Divider ........................................................................................... 386 17.4 Bus Master Clock Select Circuit ........................................................................................ 386 17.5 Subclock Input Circuit ....................................................................................................... 386 17.6 Subclock Waveform Forming Circuit................................................................................ 387 17.7 Clock Select Circuit ........................................................................................................... 387 17.8 Usage Notes ....................................................................................................................... 388 17.8.1 Note on Resonator ................................................................................................ 388 17.8.2 Notes on Board Design ......................................................................................... 388
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Section 18 Power-Down Modes.......................................................................... 389
18.1 Register Descriptions......................................................................................................... 389 18.1.1 Standby Control Register (SBYCR) ..................................................................... 390 18.1.2 Low-Power Control Register (LPWRCR) ............................................................ 392 18.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................... 393 18.2 Mode Transitions and LSI States ....................................................................................... 394 18.3 Medium-Speed Mode ........................................................................................................ 397 18.4 Sleep Mode ........................................................................................................................ 398 18.5 Software Standby Mode..................................................................................................... 399 18.6 Hardware Standby Mode ................................................................................................... 401 18.7 Watch Mode....................................................................................................................... 402 18.8 Subsleep Mode................................................................................................................... 403 18.9 Subactive Mode ................................................................................................................. 404 18.10 Module Stop Mode ............................................................................................................ 405 18.11 Direct Transitions .............................................................................................................. 405 18.12 Usage Notes ....................................................................................................................... 406 18.12.1 I/O Port Status ...................................................................................................... 406 18.12.2 Current Consumption while Waiting for Oscillation to be Stabilized .................. 406
Section 19 List of Registers................................................................................. 407
19.1 19.2 19.3 19.4 Register Addresses (Address Order).................................................................................. 408 Register Bits....................................................................................................................... 414 Register States in Each Operating Mode ........................................................................... 419 Register Select Conditions................................................................................................. 424
Section 20 Electrical Characteristics ................................................................... 431
20.1 Electrical Characteristics of H8S/2144B............................................................................ 431 20.1.1 Absolute Maximum Ratings................................................................................. 431 20.1.2 DC Characteristics................................................................................................ 432 20.1.3 AC Characteristics................................................................................................ 441 20.1.4 A/D Conversion Characteristics ........................................................................... 460 20.1.5 D/A Conversion Characteristics ........................................................................... 462 20.1.6 Flash Memory Characteristics .............................................................................. 463 20.1.7 Usage Note ........................................................................................................... 465 20.2 Electrical Characteristics of H8S/2134B ........................................................................... 466 20.2.1 Absolute Maximum Ratings................................................................................. 466 20.2.2 DC Characteristics................................................................................................ 467 20.2.3 AC Characteristics................................................................................................ 476 20.2.4 A/D Conversion Characteristics ........................................................................... 493 20.2.5 D/A Conversion Characteristics ........................................................................... 495
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20.2.6 Flash Memory Characteristics .............................................................................. 496 20.2.7 Usage Note ........................................................................................................... 498
Appendix .............................................................................................................499
A. B. C. I/O Port States in Each Processing State............................................................................. 499 Product Codes..................................................................................................................... 501 Package Dimensions........................................................................................................... 502
Index ...................................................................................................................507
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Figures
Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Overview Block Diagram of H8S/2144B ...................................................................................... 3 Block Diagram of H8S/2134B ...................................................................................... 4 Pin Arrangements of H8S/2144B .................................................................................. 5 Pin Arrangements of H8S/2134B .................................................................................. 6
Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 23 Figure 2.2 Stack Structure in Normal Mode ................................................................................. 23 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 24 Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 25 Figure 2.5 Memory Map............................................................................................................... 26 Figure 2.6 CPU Internal Registers ................................................................................................ 27 Figure 2.7 Usage of General Registers ......................................................................................... 28 Figure 2.8 Stack............................................................................................................................ 29 Figure 2.9 General Register Data Formats (1).............................................................................. 32 Figure 2.9 General Register Data Formats (2).............................................................................. 33 Figure 2.10 Memory Data Formats............................................................................................... 34 Figure 2.11 Instruction Formats (Examples) ................................................................................ 47 Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 51 Figure 2.13 State Transitions ........................................................................................................ 55 Section 3 MCU Operating Modes Figure 3.1 Address Map (1).......................................................................................................... 67 Figure 3.2 Address Map (2).......................................................................................................... 68 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3)............................................................................................ 72 Figure 4.2 Stack Status after Exception Handling ........................................................................ 74 Figure 4.3 Operation when SP Value is Odd................................................................................ 75 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 78 Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, and Registers KMIMR and KMIMRA ........................................................................ 86 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 ................................................................ 88 Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 94 Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 95 Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 97
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Figure 5.7 Interrupt Exception Handling...................................................................................... 99 Figure 5.8 Address Break Block Diagram.................................................................................. 101 Figure 5.9 Address Break Timing Example ............................................................................... 103 Figure 5.10 Conflict between Interrupt Generation and Disabling............................................. 104 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller.............................................................................. 107 Figure 6.2 IOS Signal Output Timing ........................................................................................ 114 Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 116 Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 117 Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 119 Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 120 Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)........................... 121 Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)............................ 122 Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 123 Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)......................... 124 Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) .......................... 125 Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 126 Figure 6.13 Example of Wait Cycle Insertion Timing (Pin Wait Mode).................................... 128 Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1).................... 129 Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0).................... 130 Figure 6.16 Examples of Idle Cycle Operation .......................................................................... 131 Section 8 14-Bit PWM Timer (PWMX) Figure 8.1 PWM (D/A) Block Diagram ..................................................................................... 183 Figure 8.2 PWM D/A Operation ................................................................................................ 190 Figure 8.3 Output Waveform (OS = 0, DADR corresponds to TL) ............................................ 192 Figure 8.4 Output Waveform (OS = 1, DADR corresponds to TH) ............................................ 193 Figure 8.5 D/A Data Register Configuration when CFS = 1 ...................................................... 193 Figure 8.6 Output Waveform when DADR = H'0207 (OS = 1) ................................................. 194 Section 9 16-Bit Free-Running Timer (FRT) Figure 9.1 Block Diagram of 16-Bit Free-Running Timer ......................................................... 198 Figure 9.2 Example of Pulse Output........................................................................................... 209 Figure 9.3 Increment Timing with Internal Clock Source .......................................................... 209 Figure 9.4 Increment Timing with External Clock Source......................................................... 210 Figure 9.5 Timing of Output Compare A Output ....................................................................... 210 Figure 9.6 Clearing of FRC by Compare-Match A Signal ......................................................... 211 Figure 9.7 Input Capture Input Signal Timing (Usual Case)...................................................... 211 Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) ...................... 212 Figure 9.9 Buffered Input Capture Timing ................................................................................. 212 Figure 9.10 Buffered Input Capture Timing (BUFEA = 1) ........................................................ 213
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Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 9.16 Figure 9.17 Figure 9.18 Figure 9.19
Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting .................... 214 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................... 215 Timing of Overflow Flag (OVF) Setting................................................................. 216 OCRA Automatic Addition Timing ........................................................................ 217 Timing of Input Capture Mask Signal Setting......................................................... 218 Timing of Input Capture Mask Signal Clearing ...................................................... 218 FRC Write-Clear Conflict ....................................................................................... 220 FRC Write-Increment Conflict................................................................................ 221 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used).................................................. 222 Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function is Used) ........................................................ 223 Section 10 8-Bit Timer (TMR) Figure 10.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1) .......................................... 228 Figure 10.2 Block Diagram of 8-Bit Timers (TMR_Y).............................................................. 229 Figure 10.3 Pulse Output Example ............................................................................................. 241 Figure 10.4 Count Timing for Internal Clock Input.................................................................... 242 Figure 10.5 Count Timing for External Clock Input (Both Edges) ............................................ 242 Figure 10.6 Timing of CMF Setting at Compare-Match ............................................................ 243 Figure 10.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 243 Figure 10.8 Timing of Counter Clear by Compare-Match ......................................................... 244 Figure 10.9 Timing of Counter Clear by External Reset Input................................................... 244 Figure 10.10 Timing of OVF Flag Setting.................................................................................. 245 Figure 10.11 Conflict between TCNT Write and Clear.............................................................. 249 Figure 10.12 Conflict between TCNT Write and Increment ...................................................... 250 Figure 10.13 Conflict between TCOR Write and Compare-Match ............................................ 251 Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of WDT .......................................................................................... 258 Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 265 Figure 11.3 Interval Timer Mode Operation............................................................................... 266 Figure 11.4 OVF Flag Set Timing .............................................................................................. 266 Figure 11.5 Output Timing of RESO signal ............................................................................... 267 Figure 11.6 Writing to TCNT and TCSR (WDT_0)................................................................... 268 Figure 11.7 Conflict between TCNT Write and Increment ........................................................ 269 Figure 11.8 Sample Circuit for Resetting System by RESO Signal ........................................... 270 Section 12 Serial Communication Interface (SCI and IrDA) Figure 12.1 Block Diagram of SCI............................................................................................. 272 Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 290
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Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 292 Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ............................................................................................. 293 Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 294 Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 295 Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 296 Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 297 Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 299 Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 300 Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)........................................... 302 Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 304 Figure 12.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 305 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 306 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 307 Figure 12.14 Data Format in Clock Synchronous Communication (LSB-First) ........................ 308 Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 309 Figure 12.16 Example of SCI Transmit Operation in Clock Synchronous Mode ...................... 311 Figure 12.17 Sample Serial Transmission Flowchart ................................................................. 312 Figure 12.18 Example of SCI Receive Operation in Clock Synchronous Mode ........................ 313 Figure 12.19 Sample Serial Reception Flowchart ...................................................................... 315 Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 317 Figure 12.21 IrDA Block Diagram............................................................................................. 318 Figure 12.22 IrDA Transmission and Reception ........................................................................ 319 Figure 12.23 Sample Flowchart for Mode Transition during Transmission............................... 324 Figure 12.24 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 324 Figure 12.25 Pin States during Transmission in Clock Synchronous Mode (Internal Clock) ... 325 Figure 12.26 Sample Flowchart for Mode Transition during Reception .................................... 326 Figure 12.27 Switching from SCK Pins to Port Pins.................................................................. 327 Figure 12.28 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 328 Section 13 D/A Converter Figure 13.1 Block Diagram of D/A Converter ........................................................................... 329 Figure 13.2 D/A Converter Operation Example ......................................................................... 333 Section 14 A/D Converter Figure 14.1 Block Diagram of A/D Converter ........................................................................... 336
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Figure 14.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)........................................................ 344 Figure 14.3 A/D Conversion Timing .......................................................................................... 345 Figure 14.4 External Trigger Input Timing ................................................................................ 346 Figure 14.5 A/D Conversion Accuracy Definitions.................................................................... 348 Figure 14.6 A/D Conversion Accuracy Definitions.................................................................... 348 Figure 14.7 Example of Analog Input Circuit ............................................................................ 349 Figure 14.8 Example of Analog Input Protection Circuit ........................................................... 351 Figure 14.9 Equivalent Circuit of Analog Input Pin................................................................... 352 Section 16 ROM Figure 16.1 Block Diagram of Flash Memory............................................................................ 356 Figure 16.2 Flash Memory State Transitions.............................................................................. 357 Figure 16.3 Boot Mode............................................................................................................... 358 Figure 16.4 User Program Mode (Example)............................................................................... 359 Figure 16.5 Flash Memory Block Configuration........................................................................ 360 Figure 16.6 On-Chip RAM Area in Boot Mode ......................................................................... 369 Figure 16.7 ID Code Area .......................................................................................................... 369 Figure 16.8 Programming/Erasing Flowchart Example in User Program Mode ........................ 370 Figure 16.9 Programming/Programming-Verifying Flowchart .................................................. 373 Figure 16.10 Erasing/Erasing-Verifying Flowchart.................................................................... 375 Figure 16.11 Memory Map in Programmer Mode...................................................................... 378 Section 17 Clock Pulse Generator Figure 17.1 Block Diagram of Clock Pulse Generator ............................................................... 381 Figure 17.2 Typical Connection to Crystal Resonator................................................................ 382 Figure 17.3 Equivalent Circuit of Crystal Resonator.................................................................. 382 Figure 17.4 Example of External Clock Input ............................................................................ 383 Figure 17.5 External Clock Input Timing................................................................................... 384 Figure 17.6 Timing of External Clock Output Stabilization Delay Time ................................... 385 Figure 17.7 Subclock Input Timing ............................................................................................ 387 Figure 17.8 Note on Board Design of Oscillator Circuit Section ............................................... 388 Section 18 Power-Down Modes Figure 18.1 Mode Transition Diagram ....................................................................................... 395 Figure 18.2 Medium-Speed Mode Timing ................................................................................. 398 Figure 18.3 Application Example in Software Standby Mode ................................................... 400 Figure 18.4 Hardware Standby Mode Timing ............................................................................ 401 Section 20 Electrical Characteristics Figure 20.1 Darlington Pair Driving Circuit (Example) ............................................................. 440 Figure 20.2 LED Driving Circuit (Example) .............................................................................. 441
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Figure 20.3 Output Load Circuit ................................................................................................ 441 Figure 20.4 System Clock Timing.............................................................................................. 442 Figure 20.5 Oscillation Stabilization Timing.............................................................................. 443 Figure 20.6 Oscillation Stabilization Timing (Leaving Software Standby Mode) ..................... 443 Figure 20.7 Reset Input Timing.................................................................................................. 444 Figure 20.8 Interrupt Input Timing............................................................................................. 445 Figure 20.9 Basic Bus Timing (Two-State Access).................................................................... 450 Figure 20.10 Basic Bus Timing (Three-State Access)................................................................ 451 Figure 20.11 Basic Bus Timing (Three-State Access with One Wait Cycle) ............................. 452 Figure 20.12 Burst ROM Access Timing (Two-State Access)................................................... 453 Figure 20.13 Burst ROM Access Timing (One-State Access) ................................................... 454 Figure 20.14 I/O Port Input/Output Timing................................................................................ 456 Figure 20.15 FRT Input/Output Timing ..................................................................................... 457 Figure 20.16 FRT Clock Input Timing....................................................................................... 457 Figure 20.17 8-Bit Timer Output Timing ................................................................................... 457 Figure 20.18 8-Bit Timer Clock Input Timing ........................................................................... 458 Figure 20.19 8-Bit Timer Reset Input Timing ............................................................................ 458 Figure 20.20 PWMX Output Timing.......................................................................................... 458 Figure 20.21 SCK Clock Input Timing ...................................................................................... 458 Figure 20.22 SCI Input/Output Timing (Synchronous Mode).................................................... 459 Figure 20.23 A/D Converter External Trigger Input Timing...................................................... 459 Figure 20.24 WDT Output Timing (RESO) ............................................................................... 459 Figure 20.25 Tester Measurement Condition ............................................................................. 459 Figure 20.26 Connection of VCL Capacitor............................................................................... 465 Figure 20.27 Darlington Pair Driving Circuit (Example) ........................................................... 475 Figure 20.28 LED Driving Circuit (Example)............................................................................ 476 Figure 20.29 Output Load Circuit .............................................................................................. 476 Figure 20.30 System Clock Timing............................................................................................ 477 Figure 20.31 Oscillation Stabilization Timing............................................................................ 478 Figure 20.32 Oscillation Stabilization Timing (Leaving Software Standby Mode) ................... 478 Figure 20.33 Reset Input Timing................................................................................................ 479 Figure 20.34 Interrupt Input Timing........................................................................................... 480 Figure 20.35 Basic Bus Timing (Two-State Access).................................................................. 483 Figure 20.36 Basic Bus Timing (Three-State Access)................................................................ 484 Figure 20.37 Basic Bus Timing (Three-State Access with One Wait Cycle) ............................. 485 Figure 20.38 Burst ROM Access Timing (Two-State Access)................................................... 486 Figure 20.39 Burst ROM Access Timing (One-State Access) ................................................... 487 Figure 20.40 I/O Port Input/Output Timing................................................................................ 489 Figure 20.41 FRT Input/Output Timing ..................................................................................... 490 Figure 20.42 FRT Clock Input Timing....................................................................................... 490
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Figure 20.43 Figure 20.44 Figure 20.45 Figure 20.46 Figure 20.47 Figure 20.48 Figure 20.49 Figure 20.50 Figure 20.51 Appendix Figure C.1 Figure C.2 Figure C.3 Figure C.4
8-Bit Timer Output Timing ................................................................................... 490 8-Bit Timer Clock Input Timing ........................................................................... 491 8-Bit Timer Reset Input Timing ............................................................................ 491 PWMX Output Timing.......................................................................................... 491 SCK Clock Input Timing....................................................................................... 491 SCI Input/Output Timing (Synchronous Mode).................................................... 492 A/D Converter External Trigger Input Timing...................................................... 492 Tester Measurement Condition ............................................................................. 492 Connection of VCL Capacitor............................................................................... 498
Package Dimensions (FP-100B)............................................................................... 502 Package Dimensions (TFP-100B) ............................................................................ 503 Package Dimensions (FP-80A)................................................................................. 504 Package Dimensions (TFP-80C) .............................................................................. 505
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Tables
Section 1 Overview Table 1.1 Pin Functions of H8S/2144B in Each Operating Mode ............................................ 7 Table 1.2 Pin Functions of H8S/2134B in Each Operating Mode .......................................... 11 Table 1.3 Pin Functions .......................................................................................................... 14 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 35 Table 2.2 Operation Notation ................................................................................................. 36 Table 2.3 Data Transfer Instructions....................................................................................... 37 Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 38 Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 39 Table 2.5 Logic Operations Instructions................................................................................. 40 Table 2.6 Shift Instructions..................................................................................................... 41 Table 2.7 Bit Manipulation Instructions (1)............................................................................ 42 Table 2.7 Bit Manipulation Instructions (2)............................................................................ 43 Table 2.8 Branch Instructions ................................................................................................. 44 Table 2.9 System Control Instructions.................................................................................... 45 Table 2.10 Block Data Transfer Instructions ............................................................................ 46 Table 2.11 Addressing Modes .................................................................................................. 48 Table 2.12 Absolute Address Access Ranges ........................................................................... 49 Table 2.13 Effective Address Calculation (1)........................................................................... 52 Table 2.13 Effective Address Calculation (2)........................................................................... 53 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ............................................................................ 59 Table 3.2 Pin Functions in Each Mode ................................................................................... 66 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 69 Table 4.2 Exception Handling Vector Table........................................................................... 70 Table 4.3 Status of CCR after Trap Instruction Exception Handling ..................................... 74 Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 79 Table 5.2 Correspondence between Interrupt Source and ICR ............................................... 80 Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 90 Table 5.4 Interrupt Control Modes ......................................................................................... 92 Table 5.5 Interrupt Response Times ..................................................................................... 100 Table 5.6 Number of States in Interrupt Handling Routine Execution Status ...................... 100
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Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration of H8S/2144B.......................................................................... 108 Table 6.2 Pin Configuration of H8S/2134B.......................................................................... 108 Table 6.3 Bus Specifications for Basic Bus Interface........................................................... 113 Table 6.4 Address Range for IOS Signal Output.................................................................. 115 Table 6.5 Data Buses Used and Valid Strobes...................................................................... 118 Table 6.6 Pin States in Idle Cycle......................................................................................... 132 Section 7 I/O Ports Table 7.1 Port Functions of H8S/2144B............................................................................... 134 Table 7.2 Port Functions of H8S/2134B............................................................................... 137 Table 7.3 Input Pull-Up MOS States (Port 1)....................................................................... 142 Table 7.4 Input Pull-Up MOS States (Port 2)....................................................................... 146 Table 7.5 Input Pull-Up MOS States (Port 3)....................................................................... 149 Table 7.6 Input Pull-Up MOS States (Port 6)....................................................................... 161 Table 7.7 Input Pull-Up MOS States (Port A) ...................................................................... 178 Table 7.8 Input Pull-Up MOS States (Port B) ...................................................................... 181 Section 8 14-Bit PWM Timer (PWMX) Table 8.1 Pin Configuration.................................................................................................. 184 Table 8.2 Read and Write Access Methods for 16-Bit Registers.......................................... 190 Table 8.3 Settings and Operation (Examples when = 10 MHz) ........................................ 191 Table 8.4 Position of Pulse to be Added to Basic Pulse (CFS = 1) ...................................... 195 Section 9 16-Bit Free-Running Timer (FRT) Table 9.1 Pin Configuration.................................................................................................. 199 Table 9.2 FRT Interrupt Sources .......................................................................................... 219 Table 9.3 Switching of Internal Clock and FRC Operation.................................................. 224 Section 10 8-Bit Timer (TMR) Table 10.1 Pin Configuration.................................................................................................. 230 Table 10.2 Clock Input to TCNT and Count Condition.......................................................... 233 Table 10.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 248 Table 10.4 Timer Output Priorities......................................................................................... 252 Table 10.5 Switching of Internal Clocks and TCNT Operation ............................................. 253 Section 11 Watchdog Timer (WDT) Table 11.1 Pin Configuration.................................................................................................. 259 Table 11.2 WDT Interrupt Source .......................................................................................... 267 Section 12 Serial Communication Interface (SCI and IrDA) Table 12.1 Pin Configuration.................................................................................................. 273 Table 12.2 Relationships between N Setting in BRR and Bit Rate B..................................... 282
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Table 12.3 Table 12.4 Table 12.5 Table 12.6 Table 12.7 Table 12.8 Table 12.9 Table 12.10 Table 12.11
BRR Settings for Various Bit Rates (Asynchronous Mode)................................. 283 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 287 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 287 BRR Settings for Various Bit Rates (Clock Synchronous Mode)......................... 288 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........ 288 Serial Transfer Formats (Asynchronous Mode).................................................... 291 SSR Status Flags and Receive Data Handling ...................................................... 298 IrCKS2 to IrCKS0 Bit Settings......................................................................... 320 SCI Interrupt Sources........................................................................................ 321
Section 13 D/A Converter Table 13.1 Pin Configuration.................................................................................................. 330 Table 13.2 D/A Channel Enable ............................................................................................. 332 Section 14 A/D Converter Table 14.1 Pin Configuration.................................................................................................. 337 Table 14.2 Analog Input Channels and Corresponding ADDR Registers .............................. 338 Table 14.3 A/D Conversion Time (Single Mode)................................................................... 346 Section 16 ROM Table 16.1 Differences between Boot Mode and User Program Mode .................................. 357 Table 16.2 Pin Configuration.................................................................................................. 361 Table 16.3 Operating Modes and ROM.................................................................................. 365 Table 16.4 On-Board Programming Mode Settings ............................................................... 366 Table 16.5 Boot Mode Operation ........................................................................................... 368 Table 16.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ..................................................................................................... 369 Section 17 Clock Pulse Generator Table 17.1 Damping Resistance Values ................................................................................. 382 Table 17.2 Crystal Resonator Parameters ............................................................................... 383 Table 17.3 External Clock Input Conditions........................................................................... 384 Table 17.4 External Clock Output Stabilization Delay Time ................................................. 385 Table 17.5 Subclock Input Conditions.................................................................................... 386 Section 18 Power-Down Modes Table 18.1 Operating Frequency and Wait Time.................................................................... 391 Table 18.2 LSI Internal States in Each Mode ......................................................................... 396 Section 20 Electrical Characteristics Table 20.1 Absolute Maximum Ratings ................................................................................. 431 Table 20.2 DC Characteristics (1)........................................................................................... 432 Table 20.2 DC Characteristics (2)........................................................................................... 434
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Table 20.2 Table 20.2 Table 20.3 Table 20.4 Table 20.5 Table 20.6 Table 20.7 Table 20.7 Table 20.8 Table 20.9 Table 20.10 Table 20.11 Table 20.12 Table 20.13 Table 20.14 Table 20.14 Table 20.14 Table 20.14 Table 20.15 Table 20.16 Table 20.17 Table 20.18 Table 20.19 Table 20.20 Table 20.21 Table 20.22 Table 20.23 Appendix Table A.1
DC Characteristics (3) .......................................................................................... 436 DC Characteristics (4) .......................................................................................... 438 Permissible Output Currents................................................................................. 440 Bus Driving Characteristics .................................................................................. 441 Clock Timing ........................................................................................................ 442 Control Signal Timing .......................................................................................... 444 Bus Timing (1) (Normal Mode)............................................................................ 446 Bus Timing (2) (Advanced Mode)........................................................................ 448 Timing of On-Chip Peripheral Modules ............................................................... 455 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) .................................................. 460 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion).......................................... 461 D/A Conversion Characteristics ....................................................................... 462 Flash Memory Characteristics (Programming/Erasure).................................... 463 Absolute Maximum Ratings ............................................................................. 466 DC Characteristics (1) ...................................................................................... 467 DC Characteristics (2) ...................................................................................... 469 DC Characteristics (3) ...................................................................................... 471 DC Characteristics (4) ...................................................................................... 473 Permissible Output Currents ............................................................................. 475 Clock Timing .................................................................................................... 477 Control Signal Timing ...................................................................................... 479 Bus Timing ....................................................................................................... 481 Timing of On-Chip Peripheral Modules ........................................................... 488 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) .............................................. 493 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion)............................................ 494 D/A Conversion Characteristics ....................................................................... 495 Flash Memory Characteristics (Programming/Erasure).................................... 496 I/O Port States in Each Processing State............................................................... 499
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Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions 14-bit PWM timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clock synchronous serial communication interface (SCI, IrDA) 8-bit D/A converter 10-bit A/D converter Clock pulse generator
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Section 1 Overview
* On-chip memory
ROM Flash memory version Model HD64F2144B HD64F2134B ROM 128 kbytes 128 kbytes RAM 4 kbytes 4 kbytes Remarks
* General I/O ports I/O pins: 74 (H8S/2144B) and 58 (H8S/2134B) Input-only pins: 8 * Supports various power-down modes * Compact package
Product H8S/2144B H8S/2134B Package QFP-100B TQFP-100B QFP-80A TQFP-80C Code FP-100B TFP-100B FP-80A TFP-80C 17.2 x 17.2 mm 14.0 x 14.0 mm 0.65 mm 0.5 mm Body Size 16.0 x 16.0 mm Pin Pitch 0.5 mm
Rev. 1.00 Jun.24, 2005 Page 2 of 510 REJ09B0241-0100
Section 1 Overview
1.2
Block Diagram
VCC VCL VCCB VSS VSS VSS VSS
Clock pulse generator
Internal address bus
H8S/2000 CPU
Internal data bus
Bus controller
RES XTAL EXTAL MD1 MD0 NMI STBY RESO
PA7/A23/KIN15/CIN15 PA6/A22/KIN14/CIN14 PA5/A21/KIN13/CIN13 PA4/A20/KIN12/CIN12 PA3/A19/KIN11/CIN11 PA2/A18/KIN10/CIN10 PA1/A17/KIN9/CIN9 PA0/A16/KIN8/CIN8 P27/A15 P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 P37/D15 P36/D14 P35/D13 P34/D12 P33/D11 P32/D10 P31/D9 P30/D8 PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0
P97/WAIT P96//EXCL P95/AS/IOS P94/HWR P93/RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD P52/SCK0 P51/RxD0 P50/TxD0
Port 9
ROM WDT_0, WDT_1
RAM
Port 6
16-bit FRT 14-bit PWM
8-bit timer x 3 channels
Port 4
(TMR_0, TMR_1, TMR_Y) 10-bit A/D converter SCI x 3 channels (IrDA x 1 channel)
Port 5
Port 8
Port 7
P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80
Figure 1.1 Block Diagram of H8S/2144B
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
AVref AVCC AVSS
Rev. 1.00 Jun.24, 2005 Page 3 of 510 REJ09B0241-0100
Port B
8-bit D/A converter
Port 3
Port 1
Port 2
Interrupt controller
Port A
Section 1 Overview
VCC VCL VSS VSS
Internal data bus
Bus controller
H8S/2000 CPU
Internal address bus
MD1 MD0 NMI STBY
Clock pulse generator
RES XTAL EXTAL
VSS
P27/A15 P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9
P97/WAIT P96//EXCL P95/AS/IOS P94/WR P93/RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6
Interrupt controller
Port 9
Port 2
ROM WDT_0, WDT_1
P20/A8 P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0
RAM
P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0
Port 6
P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4
16-bit FRT
P37/D7 P36/D6 P35/D5
14-bit PWM
Port 3
Port 1
P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD
Port 4
8-bit timer x 3 channels (TMR_0, TMR_1, TMR_Y)
P34/D4 P33/D3 P32/D2 P31/D1 P30/D0
10-bit A/D converter SCI x 3 channels (IrDA x 1 channel)
8-bit D/A converter
P51/RxD0 P50/TxD0
Port 5
P52/SCK0
Port 8
Port 7
AVCC
P86/IRQ5/SCK1 P85/IRQ4/RxD1
AVSS
P84/IRQ3/TxD1 P83
P77/AN7/DA1 P76/AN6/DA0 P75/AN5
P74/AN4
P73/AN3 P72/AN2 P71/AN1
P82 P81
Figure 1.2 Block Diagram of H8S/2134B
Rev. 1.00 Jun.24, 2005 Page 4 of 510 REJ09B0241-0100
P80
P70/AN0
Section 1 Overview
1.3
1.3.1
Pin Arrangements and Functions
Pin Arrangements
P42/TMRI0/SCK2
P45/TMRI1
A3/P13 A2/P12 A1/P11 A0/P10 D3/PB3 D2/PB2 D8/P30 D9/P31 D10/P32 D11/P33 D12/P34 D13/P35 D14/P36 D15/P37 D1/PB1 D0/PB0 VSS P80 P81 P82 P83 TxD1/IRQ3/P84 RxD1/IRQ4/P85 SCK1/IRQ5/P86 RESO
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50
P43/TMCI1
P47/PWX1
P46/PWX0
P44/TMO1
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
PB4/D4
PB5/D5
PB6/D6
PB7/D7
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
VCC
VSS
VSS
P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD PA0/A16/CIN8/KIN8 PA1/A17/CIN9/KIN9 AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVref P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 PA2/A18/CIN10/KIN10 PA3/A19/CIN11/KIN11 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1
RES
49 48 47 46 45 44 43 42 41 40
FP-100B TFP-100B (Top view)
39 38 37 36 35 34 33 32 31 30 29 28 27
2
XTAL
3
EXTAL
4
VCCB
5
MD1
6
MD0
7
NMI
8
STBY
26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SCK0/P52 KIN15/CIN15/A23/PA7 KIN14/CIN14/A22/PA6 RxD0/P51 TxD0/P50 KIN13/CIN13/A21/PA5 KIN12/CIN12/A20/PA4 ADTRG/IRQ2/LWR/P90 WAIT/P97 EXCL//P96 AS/IOS/P95 HWR/P94 RD/P93 IRQ0/P92 IRQ1/P91 VCL VSS
Figure 1.3 Pin Arrangements of H8S/2144B
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Section 1 Overview
A3/P13 A2/P12 A1/P11 A0/P10 D0/P30 D1/P31 D2/P32 D3/P33 D4/P34 D5/P35 D6/P36 D7/P37 VSS P80 P81 P82 P83 TxD1/IRQ3/P84 RxD1/IRQ4/P85 SCK1/IRQ5/P86
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8
FP-80A TFP-80C (Top view)
P42/TMRI0/SCK2
P45/TMRI1
P43/TMCI1
P47/PWX1
P46/PWX0
P44/TMO1
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
VCC
VSS
P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9 10 11 12 13 14 15 16 17 18 19 20
EXTAL
STBY
RES
XTAL
SCK0/P52
RxD0/P51
TxD0/P50
VSS
NMI
VCL
WAIT/P97
EXCL//P96
AS/IOS/P95
WR/P94
RD/P93
IRQ0/P92
IRQ1/P91
Figure 1.4 Pin Arrangements of H8S/2134B
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ADTRG/IRQ2/P90
MD1
MD0
Section 1 Overview
1.3.2 Table 1.1
Pin Functions in Each Operating Mode Pin Functions of H8S/2144B in Each Operating Mode
Pin Name
Pin No. FP-100B TFP-100B 1 2 3 4 5 6 7 8 9 10 (B) 11 (B) 12 13 14 15 16 17 18 19 20 (B) 21 (B) 22 23 24 25 26 Mode 1 RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL
Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL A23/PA7/CIN15/KIN15 A22/PA6/CIN14/KIN14 P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/WAIT /P96/EXCL AS/IOS HWR A21/PA5/CIN13/KIN13 A20/PA4/CIN12/KIN12 RD P92/IRQ0 P91/IRQ1 LWR/P90/IRQ2/ADTRG P60/FTCI/CIN0/KIN0
Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) RES XTAL EXTAL VCCB MD1 MD0 NMI STBY VCL PA7/CIN15/KIN15 PA6/CIN14/KIN14 P52/SCK0 P51/RxD0 P50/TxD0 VSS P97 /P96/EXCL P95 P94 PA5/CIN13/KIN13 PA4/CIN12/KIN12 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P60/FTCI/CIN0/KIN0
PA7/CIN15/KIN15 PA6/CIN14/KIN14 P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/WAIT /P96/EXCL AS/IOS HWR PA5/CIN13/KIN13 PA4/CIN12/KIN12 RD P92/IRQ0 P91/IRQ1 LWR/P90/IRQ2/ADTRG P60/FTCI/CIN0/KIN0
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Section 1 Overview
Pin Name Pin No. FP-100B TFP-100B 27 28 29 30 (B) 31 (B) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 (B) 48 (B) 49 50 51 52 53 54 Mode 1 P61/FTOA/CIN1/KIN1 P62/FTIA/CIN2/KIN2/ TMIY P63/FTIB/CIN3/KIN3 PA3/CIN11/KIN11 PA2/CIN10/KIN10 P64/FTIC/CIN4/KIN4 P65/FTID/CIN5/KIN5 P66/FTOB/CIN6/KIN6/ IRQ6 P67/CIN7/KIN7/IRQ7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/CIN9/KIN9 PA0/CIN8/KIN8 P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) P61/FTOA/CIN1/KIN1 P62/FTIA/CIN2/KIN2/ TMIY P63/FTIB/CIN3/KIN3 A19/PA3/CIN11/KIN11 A18/PA2/CIN10/KIN10 P64/FTIC/CIN4/KIN4 P65/FTID/CIN5/KIN5 P66/FTOB/CIN6/KIN6/ IRQ6 P67/CIN7/KIN7/IRQ7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS A17/PA1/CIN9/KIN9 A16/PA0/CIN8/KIN8 P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P61/FTOA/CIN1/KIN1 P62/FTIA/CIN2/KIN2/ TMIY P63/FTIB/CIN3/KIN3 PA3/CIN11/KIN11 PA2/CIN10/KIN10 P64/FTIC/CIN4/KIN4 P65/FTID/CIN5/KIN5 P66/FTOB/CIN6/KIN6/ IRQ6 P67/CIN7/KIN7/IRQ7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/CIN9/KIN9 PA0/CIN8/KIN8 P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1
Rev. 1.00 Jun.24, 2005 Page 8 of 510 REJ09B0241-0100
Section 1 Overview
Pin Name Pin No. FP-100B TFP-100B 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Mode 1 P46/PWX0 P47/PWX1 PB7/D7 PB6/D6 VCC A15 A14 A13 A12 A11 A10 A9 A8 PB5/D5 PB4/D4 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 PB3/D3 PB2/D2 D8 Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) P46/PWX0 P47/PWX1 PB7/D7 PB6/D6 VCC A15/P27 A14/P26 A13/P25 A12/P24 A11/P23 A10/P22 A9/P21 A8/P20 PB5/D5 PB4/D4 VSS VSS A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 PB3/D3 PB2/D2 D8 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P46/PWX0 P47/PWX1 PB7 PB6 VCC P27 P26 P25 P24 P23 P22 P21 P20 PB5 PB4 VSS VSS P17 P16 P15 P14 P13 P12 P11 P10 PB3 PB2 P30
Rev. 1.00 Jun.24, 2005 Page 9 of 510 REJ09B0241-0100
Section 1 Overview
Pin Name Pin No. FP-100B TFP-100B 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Note: * Mode 1 D9 D10 D11 D12 D13 D14 D15 PB1/D1 PB0/D0 VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 RESO Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) D9 D10 D11 D12 D13 D14 D15 PB1/D1 PB0/D0 VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 RESO Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P31 P32 P33 P34 P35 P36 P37 PB1 PB0 VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 RESO
The (B) in Pin No. means that the VCCB is supplied.
Rev. 1.00 Jun.24, 2005 Page 10 of 510 REJ09B0241-0100
Section 1 Overview
Table 1.2
Pin Functions of H8S/2134B in Each Operating Mode
Pin Name
Pin No. FP-80A TFP-80C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mode 1 RES XTAL EXTAL MD1 MD0 NMI STBY VCL P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/WAIT P96//EXCL AS/IOS WR RD P92/IRQ0 P91/IRQ1
Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) RES XTAL EXTAL MD1 MD0 NMI STBY VCL P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/WAIT P96//EXCL AS/IOS WR RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P60/FTCI/CIN0/KIN0 P61/FTOA/CIN1/KIN1 P62/FTIA/CIN2/KIN2/ TMIY P63/FTIB/CIN3/KIN3 P64/FTIC/CIN4/KIN4 P65/FTID/CIN5/KIN5
Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) RES XTAL EXTAL MD1 MD0 NMI STBY VCL P52/SCK0 P51/RxD0 P50/TxD0 VSS P97 P96//EXCL P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG P60/FTCI/CIN0/KIN0 P61/FTOA/CIN1/KIN1 P62/FTIA/CIN2/KIN2/ TMIY P63/FTIB/CIN3/KIN3 P64/FTIC/CIN4/KIN4 P65/FTID/CIN5/KIN5
P90/IRQ2/ADTRG P60/FTCI/CIN0/KIN0 P61/FTOA/CIN1/KIN1 P62/FTIA/CIN2/KIN2/ TMIY P63/FTIB/CIN3/KIN3 P64/FTIC/CIN4/KIN4 P65/FTID/CIN5/KIN5
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Section 1 Overview
Pin Name Pin No. FP-80A TFP-80C 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Mode 1 P66/FTOB/CIN6/KIN6/ IRQ6 P67/CIN7/KIN7/IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC A15 A14 A13 A12 A11 A10 Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) P66/FTOB/CIN6/KIN6/ IRQ6 P67/CIN7/KIN7/IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC A15/P27 A14/P26 A13/P25 A12/P24 A11/P23 A10/P22 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P66/FTOB/CIN6/KIN6/ IRQ6 P67/CIN7/KIN7/IRQ7 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VCC P27 P26 P25 P24 P23 P22
Rev. 1.00 Jun.24, 2005 Page 12 of 510 REJ09B0241-0100
Section 1 Overview
Pin Name Pin No. FP-80A TFP-80C 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Mode 1 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 Extended Modes Mode 2 (EXPE = 1) Mode 3 (EXPE = 1) A9/P21 A8/P20 VSS A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 D0 D1 D2 D3 D4 D5 D6 D7 VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1 Single-Chip Modes Mode 2 (EXPE = 0) Mode 3 (EXPE = 0) P21 P20 VSS P17 P16 P15 P14 P13 P12 P11 P10 P30 P31 P32 P33 P34 P35 P36 P37 VSS P80 P81 P82 P83 P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1
Rev. 1.00 Jun.24, 2005 Page 13 of 510 REJ09B0241-0100
Section 1 Overview
1.3.3 Table 1.3
Pin Functions Pin Functions
Pin No. [H8S/2144B] FP-100B, TFP-100B 59 9 [H8S/2134B] FP-80A, TFP80C I/O 47 8 I I
Type Power
Symbol VCC VCL
Name and Function Power supply pin. Connect this pin to the system power supply. Pin for connecting an external capacitor for the internal step-down circuit. This pin should be connected to the VSS via the external capacitor. Do not connect to the VCC. For details, see section 20, Electrical Characteristics. The power supply pin for the input/output buffers of port A. Available only for the H8S/2144B. Ground pins. Connect all the pins to the system power supply (0 V). Pins for connection to a crystal resonator. An external clock can be input on the EXTAL pin. See section 17, Clock Pulse Generator, for typical connection diagrams.
VCCB VSS Clock XTAL EXTAL
4 15, 70, 71, 92 2 3
12, 56, 73 2 3
I I I I
EXCL Operating MD1, MD0 mode control
17 17 5, 6
14 14 4, 5
O I I
Supplies the system clock to external devices. Input an external 32.768-kHz clock for the subclock. These pins set the operating mode. The relationship between these signals and the operating mode is shown below. Signal levels on these pins should not be changed during operation.
MD1 MD0 Operating Mode 0 1 Mode 1 Normal On-chip ROM disabled extended mode Mode 2 Advanced On-chip ROM enabled extended mode Single-chip mode Mode 3 Normal On-chip ROM enabled extended mode Single-chip mode
1
0
1
1
Rev. 1.00 Jun.24, 2005 Page 14 of 510 REJ09B0241-0100
Section 1 Overview
Pin No. [H8S/2144B] FP-100B, TFP-100B 1 [H8S/2134B] FP-80A, TFP80C I/O 1 I
Type System control
Symbol RES
Name and Function Reset pin. When this signal is driven low, this LSI enters the reset state.
RESO STBY Address bus
100 8
7
O I O
Outputs a reset to external devices. Available only for the H8S/2144B. When this signal is driven low, a transition is made to the hardware standby mode. Address output pins when an 16-bit access space is used. Available only for the H8S/2144B. Address output pins Bidirectional bus for data accessed in units of 8 bits or for the upper byte data accessed in units of 16 bits. Available only for the H8S/2144B. Bidirectional bus for the lower byte data accessed in units of 16 bits in the H8S/2144B. Bidirectional bus for data accessed in units of 8 bits in the H8S/2134B.
A23 to A16 10, 11, 20, 21, 30, 31, 47, 48 A15 to A0 60 to 67, 72 to 79 89 to 82
48 to 55, 57 to 64
O I/O
Data bus
D15 to D8
D7 to D0
57, 58, 68, 69, 80, 81, 90, 91
72 to 65
I/O
Bus control
WAIT
16
13
I
Requests insertion of a wait in the bus cycle when accessing the external 3-state address space. When the signal level is low, it indicates that the external address space is being read from. When the signal level is low, it indicates that the external address space is being written to. Available only for the H8S/2134B. When the signal level is low, it indicates that the external address space is being written to. The upper byte of the data bus is valid. Available only for the H8S/2144B. When the signal level is low, it indicates that the external address space is being written to. The lower byte of the data bus is valid. Available only for the H8S/2144B.
RD WR
22
17 16
O O
HWR
19
O
LWR
25
O
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Section 1 Overview
Pin No. [H8S/2144B] FP-100B, TFP-100B 18 [H8S/2134B] FP-80A, TFP80C I/O 15 O
Type Bus control
Symbol AS/IOS
Name and Function Strobe signal. When the signal level is low, it indicates that address outputs on the address bus is valid or an I/O select signal is output. Set the register to select the function to be used. Input pin for a nonmaskable interrupt request.
Interrupt signals
NMI IRQ0 to IRQ7
7
6
I
23 to 25, 97 to 99, 34, 35 26 27 34 28 29 32 33 50 53 49 52 51 54 28 55 56
18 to 20 78 to 80, 27, 28 21 22 27 23 24 25 26 40 43 39 42 41 44 23 45 46
I
Input pins for maskable interrupts.
16-bit freerunning timer (FRT)
FTCI FTOA FTOB FTIA FTIB FTIC FTID
I O O I I I I O I I I O
The counter clock input pin. The output compare A output pin. The output compare B output pin. The input capture A input pin. The input capture B input pin. The input capture C input pin. The input capture D input pin. The waveform output pins for the output compare function. Input pins for the external clock input to counters. The counter reset input pins. The counter clock input pin or reset input pin. PWM D/A pulse output pins.
8-bit timer TMO0 (TMR_0, TMO1 TMR_1, TMCI0 TMR_Y) TMCI1 TMRI0 TMRI1 TMIY 14-bit PWM timer (PWMX) Serial communication interface (SCI_0, SCI_1, SCI_2) PWX0 PWX1
TxD0 TxD1 TxD2 RxD0 RxD1 RxD2 SCK0 SCK1 SCK2
14 97 49 13 98 50 12 99 51
11 78 39 10 79 40 9 80 41
O
Transmit data output pins.
I
Receive data input pins.
I/O
Clock input/output pins. The output type is NMOS push-pull.
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Section 1 Overview
Pin No. [H8S/2144B] FP-100B, TFP-100B 49 50 [H8S/2134B] FP-80A, TFP80C I/O 39 40 28 to 21 O I I
Type SCI with IrDA (SCI_2)
Symbol IrTxD IrRxD
Name and Function Input and output pins for data encoded for IrDA use. Input pins for a matrix keyboard. Normally, P10 to P17 and P20 to P27 are used for key scanning outputs. Up to 256-key matrix (16 x 16) in the H8S/2144B or up to 128-key matrix (16 x 8) can be configured.
Keyboard [H8S/2144B] 10, 11, 20, 21, buffer 30, 31, 47, 48, KIN15 to controller 35 to 32, 29 to KIN0 26
[H8S/2134B]
KIN7 to KIN0 A/D AN7 to AN0 45 to 38 converter [H8S/2144B] 10, 11, 20, 21, 30, 31, 47, 48, CIN15 to 35 to 32, 29 to CIN0 26
[H8S/2134B]
37 to 30 28 to 21
I I
Analog input pins for the A/D converter. Extended A/D conversion input pins. Since these pins are also used as digital input/output pins, accuracy will fall.
CIN7 to CIN0 ADTRG D/A DA0 converter DA1 A/D AVCC converter D/A converter AVref 36 I 25 44 45 37 20 36 37 29 I O I Pin for input of an external trigger to start A/D conversion. Analog output pins for the D/A converter. The analog power supply pin for the A/D converter and D/A converter. When neither the A/D nor D/A converters are used, this pin should be connected to the system power supply (+5 V). The reference voltage pin for the A/D converter and D/A converter. Available only for the H8S/2144B. When neither the A/D nor D/A converters are used, this pin should be connected to the system power supply (+5 V). AVSS 46 38 I The ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V).
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Section 1 Overview
Pin No. [H8S/2144B] FP-100B, TFP-100B [H8S/2134B] FP-80A, TFP80C I/O 57 to 64 48 to 55 72 to 65 46 to 39 9 to 11 28 to 21 37 to 30 80 to 74 13 to 20 I/O I/O I/O I/O I/O I/O I I/O I/O I/O
Type I/O ports
Symbol
Name and Function 8-bit input/output pins with input pull-up MOSs. These pins can drive LED signals. 8-bit input/output pins with input pull-up MOSs. These pins can drive LED signals. 8-bit input/output pins with input pull-up MOSs. These pins can drive LED signals. 8-bit input/output pins 3-bit input/output pins 8-bit input/output pins with input pull-up MOSs 8-bit input pins 7-bit input/output pins 8-bit input/output pins 8-bit input/output pins with input pull-up MOSs. The VCCB is supplied to these pins. Available only for the H8S/2144B. 8-bit input/output pins with input pull-up MOSs. Available only for the H8S/2144B.
P17 to P10 72 to 79 P27 to P20 60 to 67 P37 to P30 89 to 82 P47 to P40 56 to 49 P52 to P50 12 to 14 P67 to P60 35 to 32 29 to 26 P77 to P70 45 to 38 P86 to P80 99 to 93 P97 to P90 16 to 19 22 to 25 PA7 to PA0 10, 11, 20, 21, 30, 31, 47, 48 PB7 to PB0 57, 58, 68, 69, 80, 81, 90, 91
I/O
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Section 2 CPU
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
* Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 CPU and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 / 8-bit register-register divide: 12 states (DIVXU.B)
CPU210A_010020020700
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Section 2 CPU
16 x 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 / 16-bit register-register divide: 20 states (DIVXU.W) * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions
Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21
In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. * Expanded address space
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Section 2 CPU
Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast.
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. * Address space Linear access to a maximum address space of 64 kbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.) * Instruction set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details on the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
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Section 2 CPU
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector (Reserved for system use)
(Reserved for system use) Exception vector table
Exception vector 1 Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC (16 bits)
SP
CCR CCR* PC (16 bits)
(a) Subroutine Branch
Note: * Ignored when returning.
(b) Exception Handling
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2
Advanced Mode
* Address space Linear access to a maximum address space of 16 Mbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. * Instruction set All instructions and addressing modes can be used. * Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4, Exception Handling.
H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved for system use)
H'00000010
Reserved Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. * Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
SP
Reserved
SP
CCR PC (24 bits)
PC (24 bits)
(a) Subroutine Branch
(b) Exception Handling
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
H'0000 64 kbytes H'FFFF 16 Mbytes Program area H'00000000
H'00FFFFFF
Data area
Not available in this LSI
H'FFFFFFFF (a) Normal Mode (b) Advanced Mode
Figure 2.5 Memory Map
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Section 2 CPU
2.4
Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers
23 PC 0
EXR* T
76543210 - - - - I2 I1 I0
76543210
CCR I UI H U N Z V C
Legend
SP PC EXR T I2 to I0 CCR I UI : Stack pointer : Program counter : Extended control register : Trace bit : Interrupt mask bits : Condition-code register : Interrupt mask bit : User bit or interrupt mask bit
H U N Z V C
: Half-carry flag : User bit : Negative flag : Zero flag : Overflow flag : Carry flag
Note: * Does not affect operation in this LSI.
Figure 2.6 CPU Internal Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.7 Usage of General Registers
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Section 2 CPU
Free area SP (ER7)
Stack area
Figure 2.8 Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Bit 7 6 to 3 2 to 0 Bit Name T -- I2 I1 I0 Initial Value R/W 0 All 1 All 1 R/W R R/W Description Trace Bit Does not affect operation in this LSI. Reserved These bits are always read as 1. Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI.
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
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Section 2 CPU
Bit 7
Bit Name I
Initial Value 1
R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.
6
UI
Undefined
R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined
R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined
R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined
R/W Negative Flag Stores the value of the most significant bit of data as a sign bit.
2
Z
Undefined
R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
1
V
Undefined
R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
0
C
Undefined
R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
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Section 2 CPU
2.4.5
Initial Register Values
The program counter (PC) among CPU internal registers is initialized when reset exception handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
2.5
Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.9 shows the data formats of general registers.
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Section 2 CPU
Data Type
1-bit data
Register Number
RnH
Data Image
7 0 Don't care 76 54 32 10
7
1-bit data RnL Don't care
0
76 54 32 10
7
4-bit BCD data RnH Upper
43
Lower
0
Don't care
7
4-bit BCD data RnL
43
Upper Lower
0
Don't care
7
Byte data RnH
0
Don't care
MSB
LSB
7
Byte data RnL
0 LSB
Don't care
MSB
Figure 2.9 General Register Data Formats (1)
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Section 2 CPU
Data Type Word data
Register Number Rn
Data Image
15
0
MSB
LSB
Word data
15
En
0
MSB
LSB
Longword data
31
ERn
16 15 0
MSB
En
Rn
LSB
[Legend] ERn En Rn RnH RnL LSB : General register ER : General register E : General register R : General register RH : General register RL : Least significant bit
MSB : Most significant bit
Figure 2.9 General Register Data Formats (2)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Image
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M + 1
MSB LSB
Longword data
Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3
MSB
LSB
Figure 2.10 Memory Data Formats
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Section 2 CPU
2.6
Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV POP* , PUSH* LDM*5, STM*5 MOVFPE* , MOVTPE*
3 3 1 1
Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L
Types 5
Arithmetic operations
ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
4
19
Logic operations Shift Bit manipulation Branch System control
AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
4 8 14 5 9 1 Total: 65
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B BIAND, BOR, BIOR, BXOR, BIXOR BCC*2, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- -- --
Block data transfer EEPMOV
Notes: B: Byte size; W: Word size; L: Longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. BCC is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5. 5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer.
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Section 2 CPU
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2
Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: *
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Instruction MOV
Data Transfer Instructions
Size*1 B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
MOVFPE MOVTPE POP
B B W/L
Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM*2 STM*
2
L L
@SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack.
Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer.
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Section 2 CPU
Table 2.4
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits.
ADDX SUBX
INC DEC ADDS SUBS DAA DAS MULXU
MULXS
B/W
Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits.
DIVXU
B/W
Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
Note:
*
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size*1 B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
CMP
B/W/L
Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
NEG
B/W/L
0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register.
EXTU
W/L
Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left.
EXTS
W/L
Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2
B
@ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
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Section 2 CPU
Table 2.5
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data.
OR
B/W/L
Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data.
XOR
B/W/L
Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
NOT
B/W/L
Rd Rd Takes the one's complement (logical complement) of data in a general register.
Note:
*
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.6
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L B/W/L Rd (rotate) Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. Rd (rotate) Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.7
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BCLR
B
0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BNOT
B
( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BTST
B
( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BAND
B
C ( of ) C Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
BIAND
B
C ( of ) C Logically ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BOR
B
C ( of ) C Logically ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
BIOR
B
C ( of ) C Logically ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
BIXOR
B
C ( of ) C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BLD
B
( of ) C Transfers a specified bit in a general register or memory operand to the carry flag.
BILD
B
( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.
BST
B
C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand.
BIST
B
C (. of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size. B: Byte
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Section 2 CPU
Table 2.8
Instruction Bcc
Branch Instructions
Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Condition Always Never CZ=0 CZ=1 C=0
JMP BSR JSR RTS
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine
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Section 2 CPU
Table 2.9
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
STC
B/W
CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
ANDC ORC XORC NOP Note: *
B B B --
CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
Size refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size -- Function if R4L 0 then Repeat @ER5 + @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5 + @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
--
2.6.2
Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields, and some have no register field. * Effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition field Specifies the branching condition of Bcc instructions.
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(1) Operation field only op NOP, RTS
(2) Operation field and register fields op rn rm ADD.B Rn, Rm
(3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16
Figure 2.11 Instruction Formats (Examples)
2.7
Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Section 2 CPU
Table 2.11 Addressing Modes
No. Addressing Mode 1 2 3 4 5 6 7 8 Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
2.7.1
Register Direct--Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn
The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn
Register Indirect with Post-Increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
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Section 2 CPU
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Register Indirect with Pre-Decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges
Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
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2.7.6
Immediate--#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.)
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Section 2 CPU
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
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Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct (Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31 0
Register indirect (@ERn)
31
24 23
0
General register contents
op 3 r
Don't care
Register indirect with displacement @(d:16,ERn) or @(d:32,ERn)
31
0
General register contents
op r disp 31
Sign extension
31 0 disp
24 23
0
Don't care
4
Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+
31
0
31
24 23
0
General register contents
Don't care
op
r 31
1, 2, or 4
* Register indirect with pre-decrement @-ERn
0
General register contents
31
24 23
0
Don't care op r
Operand Size Byte Word Longword 1, 2, or 4
Offset 1 2 4
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Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8
31
abs
24 23
87
0
op
Don't care
H'FFFF
@aa:16
31 op
abs
24 23
16 15
0
Don't care Sign extension
@aa:24 op
abs
31
24 23
0
Don't care
@aa:32
op
abs
31
24 23
0
Don't care
6
Immediate
#xx:8/#xx:16/#xx:32
Operand is immediate data.
IMM
op
7
Program-counter relative @(d:8,PC)/@(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0
disp 31
24 23
0
Don't care
8
Memory indirect @@aa:8 *
31
87 H'000000
15
Memory contents
0
abs
0 31
24 23
op
abs
16 15
0
Don't care
H'00
*
31
87 H'000000 abs
0
op
abs
31
0
Memory contents
31 24 23 Don't care
0
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Section 2 CPU
2.8
Processing States
The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. * Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, refer to section 18, Power-Down Modes.
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Section 2 CPU
Program execution state
End of exception handling Request for exception handling
SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1
SLEEP instruction with LSON = 0, SSBY = 0
Sleep mode
Interrupt request
Exception-handling state
External interrupt request
RES = high
Software standby mode
Reset state *1
STBY = high, RES = low
Hardware standby mode*2 Power-down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details, refer to section 18, Power-Down Modes.
Figure 2.13 State Transitions
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Section 2 CPU
2.9
2.9.1
Usage Notes
Note on TAS Instruction Usage
When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated in the H8S, H8/300 Series C/C++ Compiler by Renesas Technology Corp. When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1, ER4 and ER5. 2.9.2 Note on STM/LDM Instruction Usage
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by one STM/LDM instruction. The following ranges can be specified in the register list. Two registers: ER0--ER1, ER2--ER3, or ER4--ER5 Three registers: ER0--ER2 or ER4--ER6 Four registers: ER0--ER3 The STM/LDM instruction including ER7 is not generated by the H8S, H8/300 Series C/C++ Compiler by Renesas Technology Corp. 2.9.3 Note on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. Example: The BCLR instruction is executed for DDR in port 4. P47 and P46 are input pins, with a low-level signal input at P47 and a high-level signal input at P46. P45 to P40 are output pins and output low-level signals. The following shows an example in which P40 is set to be an input pin with the BCLR instruction.
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Prior to executing BCLR:
P47 Input/output Pin state DDR DR Input Low level 0 1 P46 Input High level 0 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Output Low level 1 0
BCLR instruction executed:
BCLR #0, @P4DDR The BCLR instruction is executed for DDR in port 4.
After executing BCLR:
P47 Input/output Pin state DDR DR Output Low level 1 1 P46 Output High level 1 0 P45 Output Low level 1 0 P44 Output Low level 1 0 P43 Output Low level 1 0 P42 Output Low level 1 0 P41 Output Low level 1 0 P40 Input High level 0 0
Operation: 1. When the BCLR instruction is executed, first the CPU reads P4DDR. Since P4DDR is a write-only register, so the CPU reads H'FF. In this example P4DDR has a value of H'3F, but the value read by the CPU is H'FF. 2. The CPU clears bit 0 of the read data to 0, changing data to H'FE. 3. The CPU writes H'FE to DDR, completing execution of BCLR. As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin. However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins.
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Section 2 CPU
2.9.4
EEPMOV Instruction
1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6.
R5 R6
R5 + R4L R6 + R4L
2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution).
R5 R6
R5 + R4L Invalid H'FFFF R6 + R4L
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 MCU Operating Mode Selection
This LSI has three operating modes (modes 1 to 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 lists the MCU operating modes. Table 3.1
MCU Operating Mode 0 1 2 3 1
MCU Operating Mode Selection
CPU Operating Mode -- Normal Advanced Normal On-Chip ROM -- Disabled Enabled
MD1 0
MD0 0 1 0 1
Description -- Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode Expanded mode with on-chip ROM enabled Single-chip mode
Mode 1 is an expanded mode that allows access to external memory and peripheral devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a transition can be made to external expansion mode by setting the EXPE bit in MDCR to 1. Mode 0 cannot be used in this LSI. Thus, mode pins should be set to enable mode 1, 2 or 3 in normal program execution state. Mode pins should not be changed during operation.
3.2
Register Descriptions
The following registers are related to the operating mode. For details on the bus control register (BCR), refer to section 6.3.1, Bus Control Register (BCR). * Mode control register (MDCR) * System control register (SYSCR) * Serial timer control register (STCR)
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Section 3 MCU Operating Modes
3.2.1
Mode Control Register (MDCR)
MDCR is used to set an operating mode and to monitor the current operating mode.
Bit 7 Bit Name EXPE Initial Value --* R/W
R/W*
Description Extended Mode Enable Specifies extended mode. Fixed to 1 and cannot be modified in mode 1. Readable/writable and the initial value is 0 in mode 2 or 3. 0: Single-chip mode 1: Extended mode
6 to 2 1 0
--
All 0
R
Reserved These bits are always read as 0. These bits cannot be modified.
MDS1 MDS0
--* --*
R R
Mode Select 1 and 0 These bits indicate the input levels at mode pins (MD1 and MD0) (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and MD0, respectively. These bits are read-only bits and they cannot be written to. The mode pin (MD1 and MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset.
Note:
*
The initial values are determined by the settings of the MD1 and MD0 pins.
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit 7 6 Bit Name IOSE Initial Value 0 0 R/W R/W R/W Description Reserved Although this bit is readable or writable, do not set to 1. IOS Enable Enables or disables AS/IOS pin function in extended mode. 0: AS pin Outputs low when an external area is accessed. 1: IOS pin Outputs low when a specified address of addresses H'(FF)F000 to H'(FF)F7FF is accessed. 5 4 INTM1 INTM0 0 0 R R/W Interrupt Control Select Mode 1 and 0 These bits select the control mode of the interrupt controller. For details on the interrupt control modes and interrupt control select modes 1 and 0, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset This bit indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows. 1: A reset is caused by an external reset.
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Section 3 MCU Operating Modes
Bit 2
Bit Name NMIEG
Initial Value 0
R/W R/W
Description NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input
1
HIE
0
R/W
Host Interface Enable Controls the CPU access to the keyboard matrix interrupt and input pull-up MOS control registers (KMIMR, KMPCR, and KMIMRA), and the 8-bit timer (TMR_Y) registers (TCR_Y, TCSR_Y, TCORA_Y, TCORB_Y, TCNT_Y, and TISR). 0: TMR_Y registers are accessed through an area from H'(FF)FFF0 to H'(FF)FFF7 and an area from H'(FF)FFFC to H'(FF)FFFF 1: Keyboard matrix interrupt and input pull-up MOS control registers are accessed through an area from H'(FF)FFF0 to H'(FF)FFF7 and an area from H'(FF)FFFC to H'(FF)FFFF
0
RAME
1
R/W
RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset state is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled
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Section 3 MCU Operating Modes
3.2.3
Serial Timer Control Register (STCR)
STCR enables or disables register access and on-chip flash memory, and selects the input clock of the timer counter.
Bit 7 Bit Name IICS* Initial Value 0 R/W R/W Description I2C Extra Buffer Select Specifies bits 7 to 4 of port A as open-drain output 2 buffers. These pins are used to implement an I C interface only by software. 0: PA7 to PA4 are normal input/output pins. 1: PA7 to PA4 are input/output pins enabling bus driving. 6, 5 4 IICE All 0 0 R/W R/W Reserved These bits should not be changed. I2C Master Enable Enables or disables the CPU access to the PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), and SCI registers (SMR, BRR, SCMR). 0: SCI_1 registers are accessed through an area from H'(FF)FF88 to H'(FF)FF89 and an area from H'(FF)FF8E to H'(FF)FF8F. SCI_2 registers are accessed through an area from H'(FF)FFA0 to H9'(FF)FFA1 and an area from H'(FF)FFA6 to H'(FF)FFA7. SCI_0 registers are accessed through an area from H'(FF)FFD8 to H'(FF)FFD9 and an area from H'(FF)FFDE to H'(FF)FFDF. 1: No are accessed through an area from H'(FF)FF88 to H'(FF)FF89 and an area from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed through an area from H'(FF)FFA0 to H'(FF)FFA1 and an area from H'(FF)FFA6 to H'(FF)FFA7. No registers are accessed through an area from H'(FF)FFD8 to H'(FF)FFD9 and through an area from H'(FF)FFDE to H'(FF)FFDF.
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Section 3 MCU Operating Modes
Bit 3
Bit Name FLSHE
Initial Value 0
R/W R/W
Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers in power-down state (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (PCSR, SYSCR2). 0: Registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. 1: Control registers of flash memory are accessed in an area from H'(FF)FF80 to H'(FF)FF87.
2 1 0
-- ICKS1 ICKS0
0 0 0
R/(W) R/W R/W
Reserved The initial value should not be changed. Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, refer to section 10.3.4, Timer Control Register (TCR).
Note:
*
Available only for the H8S/2144B.
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Section 3 MCU Operating Modes
3.3
3.3.1
Operating Mode Descriptions
Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled. Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus. 3.3.2 Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset. Ports 1, 2 and A output an address by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B functions as a data bus when the ABW bit in WSCR is cleared to 0. 3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The CPU can access a 56-kbyte address space in mode 3. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B functions as a data bus when the ABW bit in WSCR is cleared to 0. 3.3.4 Pin Functions in Each Operating Mode
Pin functions of ports 1 to 3, 9, A, and B depend on the operating mode. Table 3.2 shows pin functions in each operating mode.
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Section 3 MCU Operating Modes
Table 3.2
Port Port 1 Port 2 Port A*2 Port 3 Port B* Port 9
2
Pin Functions in Each Mode
Mode 1 A A P D P* /D P97 P96 P95 to P93 P92 to P91 P90 P*1/C C*1/P C P P* /C
1 1
Mode 2 P* /A P*1/A P*1/A P* /D P* /D P*1/C P*1/C P*1/C P P* /C
1 1 1 1
Mode 3 P*1/A P*1/A P P*1/D P*1/D P*1/C P*1/C P*1/C P P*1/C
[Legend] P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. Immediately after a reset. 2. Available only for the H8S/2144B.
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Section 3 MCU Operating Modes
3.4
Address Map in Each Operating Mode
Figures 3.1 and 3.2 show the address map in each operating mode.
Mode 1 Normal mode Extended on-chip ROM disabled mode H'0000
Mode 2 (EXPE = 1) Advanced mode Extended on-chip ROM enabled mode H'000000
H'000000
Mode 2 (EXPE = 0) Advanced mode Single-chip mode
External address space
On-chip ROM
On-chip ROM
H'01FFFF H'020000
H'E080 On-chip RAM*1
H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)*1 Internal I/O registers 1
H'01FFFF
External address space*2
H'FFE080
H'FFE080 On-chip RAM*1 H'FFEFFF H'FFF000 H'FFF7FF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
On-chip RAM
H'FFEFFF
External address space*2 Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)*1 Internal I/O registers 1
H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1
Notes: 1. These areas can be used as an external address space by clearing bit RAME in SYSCR to 0. 2. Since there are only 16 bits of address bus in the H8S/2134B, only the area where the I/O select function is set can be accessed.
Figure 3.1 Address Map (1)
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Section 3 MCU Operating Modes
Mode 3 (EXPE = 1) Normal mode Extended on-chip ROM enabled mode
Mode 3 (EXPE = 0) Normal mode Single-chip mode
H'0000
H'0000
On-chip ROM
On-chip ROM
H'DFFF
External address space
H'E080 On-chip RAM*
H'EFFF H'F000 H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF
H'DFFF
H'E080 On-chip RAM H'EFFF
External address space Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes)* Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1
Note: * These areas can be used as an external address space by clearing bit RAME in SYSCR to 0.
Figure 3.2 Address Map (2)
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Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
Exception handling is caused by a reset, interrupt, direct transition, or trap instruction as shown in table 4.1. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Start of Exception Handling Starts immediately after the signal level on the RES pin changes from low to high or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direct transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in program execution state.
Interrupt
Direct transition Trap instruction Low
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Section 4 Exception Handling
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table
Vector Address Exception Source Reset Reserved for system use Vector Number 0 1 5 6 7 8 9 10 11 Reserved for system use 12 15 16 17 18 19 20 21 22 23 24 107 Normal Mode H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00DE to H'00DF Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 H'0001BC to H'0001BF
Direct transition External interrupt (NMI) Trap instruction (four sources)
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Internal interrupt*
Note:
*
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table.
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Section 4 Exception Handling
4.3
Reset
The reset exception handling is given the highest priority. When the RES signal goes low, all processing halts and this LSI enters the reset state. When the power is turned on, hold the RES signal low for at least 20 ms to ensure that this LSI is reset. To reset this LSI during operation, hold the RES signal low for at least 20 cycles. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI can also be reset by an overflow of the watchdog timer. For details, see section 11, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling
When the RES signal goes high after being held low for a given time, this LSI starts the reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit is set to 1 in CCR. 2. The vector address of the reset exception handling is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence.
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Section 4 Exception Handling
Vector fetch
Internal Prefetch of first program processing instruction
RES
Internal address bus
(1)
(3)
Internal read signal
Internal write signal
High
Internal data bus
(2)
(4)
(1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First program instruction
Figure 4.1 Reset Sequence (Mode 3) 4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset is Released
After a reset is released, the module stop control registers (MSTPCR) are initialized, and all modules are in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, leave the module stop mode.
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Section 4 Exception Handling
4.4
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, and KIN15 to KIN0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address.
4.5
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved to the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
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Section 4 Exception Handling
Table 4.3
Status of CCR after Trap Instruction Exception Handling
CCR
Interrupt Control Mode 0 1 [Legend] 1: Set to 1 --: Retains value prior to execution
I 1 1
UI -- 1
4.6
Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
Normal mode
Advanced mode
SP
CCR CCR* PC (16 bits)
SP
CCR PC (24 bits)
Note: Ignored on return.
Figure 4.2 Stack Status after Exception Handling
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Section 4 Exception Handling
4.7
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn (or MOV.W @SP+, Rn)
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what happens when the SP value is odd.
Address
CCR
SP
PC
SP
R1L
H'FFEFFA H'FFEFFB
PC
H'FFEFFC H'FFEFFD
SP
H'FFEFFF
TRAPA instruction executed SP set to H'FFFEFF Legend
MOV.B R1L, @-ER7 executed Contents of CCR lost
Data saved above SP
CCR : PC : R1L : SP :
Condition code register Program counter General register R1L Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode.
Figure 4.3 Operation when SP Value is Odd
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Section 4 Exception Handling
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Features
* Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * 23 external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be selected for IRQ7 to IRQ0. The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt inputs (KIN7 to KIN0), and the IRQ7 interrupt is shared by the interrupt from the IRQ7 pin and sixteen external interrupt inputs (KIN15 to KIN8). KIN15 to KIN0 can be masked individually by the user program.
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Section 5 Interrupt Controller
INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input IRQ input ISR ISCR
KMIMR
CPU
Interrupt request Vector number Priority check
IER
I, UI
KIN input
KIN input
CCR
Internal interrupt request WOVI0 to TEI2
ICR Interrupt controller
[Legend] ICR: ISCR: IER: ISR: KMIMR: SYSCR:
Interrupt control register IRQ sense control register IRQ enable register IRQ status register Keyboard matrix interrupt mask register System control register
Figure 5.1 Block Diagram of Interrupt Controller
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Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller. Table 5.1
Symbol NMI IRQ7 to IRQ0
Pin Configuration
I/O Input Input Function Nonmaskable external interrupt Rising edge or falling edge can be selected Maskable external interrupts Rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin.
KIN15 to KIN0 (KIN7 to KIN0)* Note: * H8S/2134B
Input
Maskable external interrupts Falling edge or level sensing can be selected.
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). * * * * * * * Interrupt control registers A to C (ICRA to ICRC) Address break control register (ABRKCR) Break address registers A to C (BARA to BARC) IRQ sense control registers (ISCRH, ISCRL) IRQ enable register (IER) IRQ status register (ISR) Keyboard matrix interrupt mask registers (KMIMRA, KMIMR)
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Section 5 Interrupt Controller
5.3.1
Interrupt Control Registers A to C (ICRA to ICRC)
The ICR registers set interrupt control levels for interrupts other than NMI and address breaks. The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.
Bit 7 to 0 Bit Name ICRn7 to IRCn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) n: A to C
Table 5.2
Correspondence between Interrupt Source and ICR
Register
Bit 7 6 5 4 3 2 1 0 n: :
Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0
ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 -- WDT_0 WDT_1
ICRB A/D converter FRT -- -- TMR_0 TMR_1 TMR_Y --
ICRC SCI_0 SCI_1 SCI_2 -- -- -- -- --
A to C Reserved. The write value should always be 0.
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Section 5 Interrupt Controller
5.3.2
Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an address break is requested.
Bit 7 Bit Name CMF Initial Value 0 R/W R Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE flag is set to 1. [Clearing condition] When an exception handling is executed for an address break interrupt. 6 to 1 0 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. BIE 0 R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled
5.3.3
Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. * BARA
Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
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Section 5 Interrupt Controller
* BARB
Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus.
* BARC
Bit 7 to 1 0 Bit Name A7 to A1 -- Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 R Reserved This bit is always read as 0 and cannot be modified.
5.3.4
IRQ Sense Control Registers (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. * ISCRH
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 7 to 4)
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Section 5 Interrupt Controller
* ISCRL
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 3 to 0)
5.3.5
IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1.
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Section 5 Interrupt Controller
5.3.6
IRQ Status Register (ISR)
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Description [Setting condition] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * * When reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn input is high (n = 7 to 0) When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set
*
Note:
*
Only 0 can be written, for flag clearing.
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Section 5 Interrupt Controller
5.3.7
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
KMIMRA and KMIMR mask each key-sensing input (KIN15 to KIN0) interrupt. To make the settings of these registers valid, clear bit MSTP2 in MSTPCRL to 0. * KMIMRA
Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask 15 to 8 These bits enable or disable a key-sensing input interrupt request (KIN15 to KIN8). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request
Note: Bits KMIMR15 to KMIMR8 should not be cleared to 0 in the H8S/2134B.
* KMIMR
Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial Value 1 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask 7 to 0 These bits enable or disable a key-sensing input interrupt request (KIN7 to KIN0). KMIMR6 also performs interrupt request mask control for pin IRQ6. 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request
Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, and KMIMRA and KMIMR.
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Section 5 Interrupt Controller
KMIMR0 (initial value 1) P60/KIN0
KMIMR5 (initial value 1) P65/KIN5 KMIMR6 (initial value 0) P66/KIN6/IRQ6 KMIMR7 (initial value 1) P67/KIN7/IRQ7
IRQ6 internal signal Edge level selection enable/disable circuit IRQ6 interrupt
IRQ6E IRQ6SC
KMIMR8 (initial value 1) PA0/KIN8 KMIMR9 (initial value 1) PA1/KIN9 KMIMR15 (initial value 1) PA7/KIN15
IRQ7 internal signal Edge level selection enable/disable circuit IRQ7 interrupt
IRQ7E IRQ7SC
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, and Registers KMIMR and KMIMRA If any of bits KMIMR15 to KMIMR8 is cleared to 0, an interrupt input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins, either low-level sensing or falling-edge sensing must be specified as the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7).
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Section 5 Interrupt Controller
5.4
5.4.1
Interrupt Sources
External Interrupts
There are three types of external interrupts: NMI, IRQ7 to IRQ0 and KIN15 to KIN0. KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * Interrupt control levels can be specified by the ICR settings. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 to use the pin as an I/O pin for another function. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
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Section 5 Interrupt Controller
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input n = 7 to 0 Clear signal S R Q IRQn interrupt request
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0. When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will be ignored. Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied, regardless of the IER setting, refer to a needed flag only. KIN15 to KIN0 Interrupts: Interrupts KIN15 to KIN0 are requested by input signals on pins KIN15 to KIN0. When pins KIN15 to KIN0 are used as key-sense inputs, clear a corresponding bit in KMIMR to 0 in order to enable their key-sense input interrupts. Remaining unused bits in KMIMR should be set to 1 in order to disable interrupts. Interrupts KIN15 to KIN8 are requested as an IRQ7 interrupt, and interrupts KIN7 to KIN0 are requested as an IRQ6 interrupt. The pin function, conditions of enabling or disabling interrupts, interrupt sense condition, and interrupt indicating method to generate a key-sense input interrupt depend on those for the IRQ7 or IRQ6 interrupt. When pins KIN7 to KIN0, or KIN15 to KIN8 are used as key-sense interrupt input pins, either low-level sensing or falling-edge sensing must be specified as the interrupt sense condition for the corresponding interrupt source (IRQ6 or IRQ7).
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Section 5 Interrupt Controller
5.4.2
Internal Interrupts
Internal interrupts issued from the on-chip peripheral modules have the following features: 1. For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. 2. The priority level for each interrupt can be set by ICR.
5.5
Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to control level 0 (no priority).
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Section 5 Interrupt Controller
Table 5.3
Origin of Interrupt Source
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address Name Vector Normal Number Mode 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 to 47 48 49 50 51 52 53 54 55 56 to 63 64 65 66 67 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A to H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 to H'007E H'0080 H'0082 H'0084 H'0086 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 to H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 to H'0000FC H'000100 H'000104 H'000108 H'00010C ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 -- ICRA1 ICRA0 -- ICRB7 -- Priority High
External pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8 -- WDT_0 WDT_1 -- A/D converter -- Reserved for system use WOVI0 (Interval timer) WOVI1 (Interval timer) Address break ADI (A/D conversion end) Reserved for system use
FRT
ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use Reserved for system use
ICRB6
--
--
TMR_0
CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflow) Reserved for system use
ICRB3
Low
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Section 5 Interrupt Controller
Origin of Interrupt Source TMR_1
Vector Address Name CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) Reserved for system use Reserved for system use Vector Normal Number Mode 68 69 70 71 72 73 74 75 76 to 79 80 81 82 83 84 85 86 87 88 89 90 91 92 to 111 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 to H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 H'00B8 to H'00DE Advanced Mode H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 to H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 H'000164 H'000168 H'00016C H'000170 to H'0001BC ICR ICRB2 Priority High
TMR_Y
ICRB1
--
--
SCI_0
ERI0 (Reception error 0) RXI0 (Reception completion 0) TXI0 (Transmission data empty 0) TEI0 (Transmission end 0) ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) Reserved for system use
ICRC7
SCI_1
ICRC6
SCI_2
ICRC5
--
-- Low
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Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.4 Interrupt Control Modes
Priority Setting Registers ICR Interrupt Mask Bits I
SYSCR Interrupt Control Mode INTM1 INTM0 0 0 0
Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I bit. Priority levels can be set with ICR.
1
1
ICR
I, UI
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than NMI and address breaks are masked by ICR and the I bit of the CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine.
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Section 5 Interrupt Controller
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Section 5 Interrupt Controller
Program excution state
Interrupt generated? Yes Yes
No
NMI No
An interrupt with interrupt control level 1?
No
Hold pending
Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 TEI2 Yes Yes TEI2 Yes No No
I=0 Yes
No
Save PC and CCR
I
1
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. * An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending * An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRC are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to control level 1, and other interrupts are set to control level 0) is shown below. Figure 5.5 shows a state transition diagram. * All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...) * Only NMI, IRQ2, IRQ3 and address break interrupt requests are accepted when I = 1 and UI = 0. * Only an NMI and address break interrupt request is accepted when I = 1 and UI = 1.
I All interrupt requests are accepted I
0 0
1, UI
Only NMI, address break, IRQ2, and IRQ3 interrupt requests are accepted
I Exception handling execution or I 1, UI 1
0
UI
0
Exception handling execution or UI 1
Only NMI and address break interrupt requests are accepted
Figure 5.5 State Transition in Interrupt Control Mode 1 Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
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Section 5 Interrupt Controller
3.
4. 5.
6. 7.
interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When both the I and UI bits are set to 1, only an NMI or address break interrupt request is accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit is not affected. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address break interrupt. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Section 5 Interrupt Controller
Program excution state No
Interrupt generated? Yes Yes
NMI No
An interrupt with interrupt control level 1?
No
Hold pending
Yes No No IRQ1 Yes TEI2 Yes No IRQ0 Yes IRQ1 Yes TEI2 Yes No
IRQ0 Yes
I=0
Yes
No
I=0 No Yes
No
UI = 0 Yes
Save PC and CCR
I
1, UI
1
Read vector address Branch to interrupt handling routine
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1
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Section 5 Interrupt Controller
5.6.3
Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
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Interrupt is accepted
Interrupt level decision and wait for end of instruction Instruction prefetch Stack access Vector fetch Internal processing Internal processing
Prefetch of instruction in interrupt-handling routine
Interrupt request signal
Internal address bus
(1)
(3)
(5)
(7)
(9)
(11)
(13)
Internal read signal
Internal write signal
Figure 5.7 Interrupt Exception Handling
(2)
Internal data bus
(4)
(6)
(8)
(10)
(12)
(14)
(1)
Section 5 Interrupt Controller
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(6) (8) (9) (11) (10) (12) (13) (14)
(2) (4) (3) (5) (7)
Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.) SP - 2 SP - 4
Saved PC and CCR Vector address Starting address of interrupt-handling routine (contents of vector address) Starting address of interrupt-handling routine ((13) = (10) (12)) First instruction in interrupt-handling routine
REJ09B0241-0100
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.5 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times
Normal Mode
1
No. Execution Status 1 2 3 4 5 6 Interrupt priority determination*
Advanced Mode 3 1 to (19 + 2*SI)
Number of wait states until executing instruction ends*2 PC, CCR stack save Vector fetch Instruction fetch*
3 4
2*SK SI
2*SK 2*SI 2*SI 2
Internal processing*
Total (using on-chip memory) Notes: 1. 2. 3. 4.
11 to 31
12 to 32
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.6
Number of States in Interrupt Handling Routine Execution Status
Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m
Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK
Internal Memory 1
2-State Access 4
3-State Access 6 + 2m
[Legend] m: Number of wait states in external device access
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Section 5 Interrupt Controller
5.7
5.7.1
Address Break
Features
This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address break interrupt exception handling is performed. With this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. 5.7.2 Block Diagram
Figure 5.8 shows a block diagram of the address break.
BAR
ABRKCR
Comparator
Match signal
Control logic
Address break interrupt request
Internal address Prefetch signal (internal signal)
Figure 5.8 Address Break Block Diagram 5.7.3 Operation
If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. When an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the CPU is invalid to an address break interrupt. To use the address break function, set each register as follows: 1. Set a break address in the A23 to A1 bits in BAR.
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Section 5 Interrupt Controller
2. Set the BIE bit in ABRKCR to 1 to enable the address break. When the BIE bit is cleared to 0, an address break is not requested. When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an interrupt. The interrupt source should be determined by the interrupt handling routine if necessary. 5.7.4 Usage Notes
1. In an address break, the break address should be an address where the first byte of the instruction exists. Otherwise, a break condition will not be satisfied. 2. In normal mode, addresses A23 to A16 are not compared. 3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and RTE instruction are placed immediately prior to the address specified by BAR, a prefetch signal to the address may be output to request an address break by executing these instruction. It is necessary to take countermeasures: do not set a break address to an address immediately after these instructions, or determine whether interrupt handling is performed by satisfaction of a normal condition. 4. An address break interrupt is generated by combining the internal prefetch signal and an address. Therefore, the timing to enter the interrupt exception handling differs according to the instructions at the specified and at prior addresses and execution cycles. Figure 5.9 shows an example of address timing.
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Section 5 Interrupt Controller
(1) When a break address specified instruction is executed for one state in the program area and on-chip memory
Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation
Save to stack
Vector fetch
Internal Instruction operation fetch
Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036
NOP NOP execution execution
NOP execution
Interrupt exception handling
Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Break point NOP instruction is executed at break point address H'0312 and following address H'0314. Fetching is performed from address H'0316 after exception handling ends.
(2) When a break address specified instruction is executed for two states in the program area and on-chip memory
Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation
Save to stack
Vector fetch
Internal operation
Instruction fetch
Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036
NOP execution
MOV.W execution
Interrupt exception handling
Break request signal H'0310 H'0312 H'0316 H'0318 NOP MOV.W #xx:16,Rd NOP NOP Break point MOV instruction is executed at break point address H'0312, and NOP instruction is not executed at the following address H'0314. Fetching is performed from address H'0316 after exception handling ends.
(3) When a break address specified instruction is executed for one state in the program area and external memory (2-state access, 16-bit bus access) Instruction fetch Address bus H'0310 H'0312 H'0314 SP-2 SP-4 H'0036 Instruction fetch Instruction fetch
Internal operation
Save to stack
Vector fetch
Instruction fetch
NOP execution Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Break point
Interrupt exception handling
NOP instruction is not executed at break point address H'0312. Fetching is performed from address H'0312 after exception handling ends.
Figure 5.9 Address Break Timing Example
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Section 5 Interrupt Controller
5.8
5.8.1
Usage Notes
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.10 shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
TCR write cycle by CPU
CMIA exception handling
Internal address bus
TCR address
Internal write signal
CMIEA
CMFA
CMIA interrupt signal
Figure 5.10 Conflict between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
5.8.2
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
5.8.4
IRQ Status Register (ISR)
According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset to write 0. (n = 7 to 0)
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Section 5 Interrupt Controller
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Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that can specify the bus settings such as the bus width and the number of access cycles of the external address space.
6.1
Features
* Basic bus interface 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area * Burst ROM interface A burst ROM interface can be set for basic expansion areas 1-state access or 2-state access can be selected for burst access * Idle cycle insertion An idle cycle can be inserted for external write cycles immediately after external read cycles
External bus control signals
Bus controller
Internal control signals
Bus mode signal
BCR
WAIT
Wait controller
Figure 6.1 Block Diagram of Bus Controller
BSCS20AA_000020020700
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Internal data bus
WSCR
Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Tables 6.1 and 6.2 summarize the pin configuration of the bus controller. Table 6.1
Symbol AS IOS RD HWR
Pin Configuration of H8S/2144B
I/O Output Output Output Output Function Strobe signal indicating that address output on the address bus is valid (when the IOSE bit in SYSCR is cleared to 0). I/O select signal (when the IOSE bit in SYSCR is set to 1). Strobe signal indicating that the external address space is being read. Strobe signal indicating that the external address space is being written to, and the upper byte (D15 to D8) of the data bus is valid. Strobe signal indicating that the external address space is being written to, and the lower byte (D7 to D0) of the data bus is valid. Wait request signal when accessing the external 3-state access space.
LWR
Output
WAIT
Input
Table 6.2
Symbol AS IOS RD WR WAIT
Pin Configuration of H8S/2134B
I/O Output Output Output Output Input Function Strobe signal indicating that address output on the address bus is valid (when the IOSE bit in SYSCR is cleared to 0). I/O select signal (when the IOSE bit in SYSCR is set to 1). Strobe signal indicating that the external address space is being read. Strobe signal indicating that the external address space is being written to, and the data bus (D7 to D0) is valid. Wait request signal when accessing the external 3-state access space.
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Section 6 Bus Controller (BSC)
6.3
Register Descriptions
The bus controller has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). * Bus control register (BCR) * Wait state control register (WSCR) 6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space or the I/O area range when the AS/IOS pin is specified as an I/O strobe pin.
Bit 7 6 Bit Name -- ICIS0 Initial Value 1 1 R/W R/W R/W Description Reserved This bit should not be written by 0. Idle Cycle Insertion Selects whether or not to insert 1-state of the idle cycle between bus cycles when the external write cycle follows the external read cycle. 0: Idle cycle not inserted when the external write cycle follows the external read cycle 1: 1-state idle cycle inserted when the external write cycle follows the external read cycle 5 BRSTRM 0 R/W Burst ROM Enable Selects the bus interface for the external address space. 0: Basic bus interface 1: Burst ROM interface 4 BRSTS1 1 R/W Burst Cycle Select 1 Selects the number of cycles in the burst cycle of the burst ROM interface. 0: 1 cycle 1: 2 cycles
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Section 6 Bus Controller (BSC)
Bit 3
Bit Name BRSTS0
Initial Value 0
R/W R/W
Description Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface. 0: Max, 4 words 1: Max, 8 words
2 1 0
IOS1 IOS0
0 1 1
R/W R/W R/W
Reserved This bit should not be written by 0. IOS Select 1, 0 Select the address range where the IOS signal is output. For details, refer to table 6.4, Address Range for IOS Signal Output.
6.3.2
Wait State Control Register (WSCR)
WSCR is used to specify the data bus width for external address space access, the number of access cycles, the wait mode, and the number of wait cycles for access to external address spaces. The bus width and the number of access cycles for internal memory and internal I/O registers are fixed regardless of the WSCR settings.
Bit 7 6 5 Bit Name -- -- ABW Initial Value 0 0 1 R/W R/W R/W R/W Description Reserved These bits should not be written by 1. Bus Width Control Selects 8 or 16bits for access to the external address space. 0: 16-bit access space* 1: 8-bit access space
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Section 6 Bus Controller (BSC)
Bit 4
Bit Name AST
Initial Value 1
R/W R/W
Description Access State Control Selects 2 or 3 access cycles for access to the external address space. This bit also enables or disables waitcycle insertion. 0: 2-state access space. Wait cycle insertion disabled in external address space access 1: 3-state access space. Wait cycle insertion enabled in external address space access
3 2
WMS1 WMS0
0 0
R/W R/W
Wait Mode Select 1, 0 Select the wait mode for access to the external address space when the AST bit is set to 1. 00: Program wait mode 01: Wait disabled mode 10: Pin wait mode 11: Pin auto-wait mode
1 0
WC1 WC0
1 1
R/W R/W
Wait Count 1, 0 Select the number of program wait cycles to be inserted when the external address space is accessed while the AST bit is set to 1. 00: Program wait cycle is not inserted 01: 1 program wait cycle is inserted 10: 2 program wait cycles are inserted 11: 3 program wait cycles are inserted
Note:
*
Setting prohibited in the H8S/2134B.
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Section 6 Bus Controller (BSC)
6.4
6.4.1
Bus Control
Bus Specifications
The external address space bus specifications consist of three elements: Bus width, the number of access cycles, and the wait mode and the number of program wait cycles. The bus width and the number of access cycles for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller settings. Bus Width: A bus width of 8 or 16 bits can be selected by the ABW bit in WSCR. Note that the 16-bit bus width cannot be set in the H8S/2134B. Number of Access Cycles: Two or three access cycles can be selected via the AST bit in WSCR. When the 2-state access space is designated, wait-cycle insertion is disabled. In the burst ROM interface, the number of access cycles is determined regardless of the AST bit setting. Wait Mode and Number of Program Wait Cycles: When a 3-state access space is designated by the AST bit in WSCR, the wait mode and the number of program wait cycles to be inserted automatically is selected by the WMS1, WMS0, WC1, and WC0 bits in WSCR. From 0 to 3 program wait cycles can be selected.
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Section 6 Bus Controller (BSC)
Table 6.3 shows the bus specifications for the basic bus interface of each area. Table 6.3 Bus Specifications for Basic Bus Interface
Bus Specifications ABW 0 AST 0 1 WMS1 WMS0 WC1 -- 0 --* -- 1 --* -- -- 0 WC0 -- -- 0 1 1 0 1 1 0 1 -- 0 --* -- 1 --* -- -- 0 -- -- 0 1 1 Note: * 0 1 Other than WMS1 = 0 and WMS0 = 1 8 8 2 3 3 Bus Width 16 16 Number of Number of Program Access Cycles Wait Cycles 2 3 3 0 0 0 1 2 3 0 0 0 1 2 3
6.4.2
Advanced Mode
The external address space is initialized to the basic bus interface and a 3-state access space. In onchip ROM enabled extended mode, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The onchip RAM and its reserved area are enabled when the RAME bit in SYSCR is set to 1. They are disabled and corresponding addresses are the external address space when the RAME bit is cleared to 0. In the H8S/2134B, the upper address in advanced mode (A16 to A23) cannot be output since there are only 16 address output pins. However, an area from H'FFF000 to H'FFF7FF can be accessed using the AS/IOS signal specified as the I/O select signal. Therefore, the area can be accessed even when the H8S/2134B operates in ROM disabled extended and advanced mode.
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Section 6 Bus Controller (BSC)
6.4.3
Normal Mode
The external address space is initialized as the basic bus interface and a 3-state access space. In on-chip ROM disable extended mode, the address space other than on-chip RAM and internal I/O registers is specified as the external address space. In on-chip ROM enable extended mode, the address space other than on-chip ROM, on-chip RAM, internal I/O registers, and their reserved areas is specified as the external address space. The on-chip RAM area is enabled when the RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the RAME bit is cleared to 0. 6.4.4 I/O Select Signals
The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Bus cycle T1
T2
T3
Address bus
External addresses selected by IOS
IOS
Figure 6.2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE bit to 1. For details, refer to section 7, I/O Ports. The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR, as shown in table 6.4.
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Section 6 Bus Controller (BSC)
Table 6.4
IOS1 0
Address Range for IOS Signal Output
IOS0 0 1 IOS Signal Output Range H'(FF)F000 to H'(FF)F03F H'(FF)F000 to H'(FF)F0FF H'(FF)F000 to H'(FF)F3FF H'(FF)F000 to H'(FF)F7FF (Initial value)
1
0 1
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Section 6 Bus Controller (BSC)
6.5
Basic Bus Interface
The basic bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications when using the basic bus interface, see table 6.3 6.5.1 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used when the external address space is accessed, according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. In the H8S/2134B, eight bits of the data bus are available (D7 to D0) and only the 8-bit access space is settable. Therefore, data alignment described in this section is not performed.
Upper data bus Lower data bus D15 D8 D7 D0
Byte size
1st bus cycle
2nd bus cycle
1st bus cycle
Word size
Longword size
2nd bus cycle 3rd bus cycle 4th bus cycle
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space (Not available for the H8S/2134B): Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
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Section 6 Bus Controller (BSC)
Upper data bus Lower data bus D15 D8 D7 D0
Byte size
Byte size * Even address
* Odd address
Word size
Longword size
1st bus cycle 2nd bus cycle
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes
Table 6.5 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower bytes of the data bus. In a write, the HWR signal is valid for the upper byte of the data bus, and the LWR signal for the lower byte. In the H8S/2134B, only eight bits of the data bus is valid (D7 to D0). The strobe signals corresponding to the 8-bit data bus are the RD and WR signal. The WR signal in the H8S/2134B is the equivalent of the HWR signal in the H8S/2144B.
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Section 6 Bus Controller (BSC)
Table 6.5
Data Buses Used and Valid Strobes
H8S/2144B Access Read/ Size Write Byte Read Write Valid Address Strobe -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD RD HWR (WR) RD Valid Invalid Valid Undefined Valid H8S/2134B
Area 8-bit access space
Upper Data Lower Data Bus (D15 to Bus (D7 to Data Bus D8) D0) (D7 to D0) Valid Ports or others Ports or others Invalid Valid Undefined Valid Valid Valid Valid Invalid Valid Undefined Valid Valid Valid
16-bit access space [H8S/2144B]
Byte
Read
HWR, LWR Valid
Note:
*
Undefined: Undefined data is output. Invalid: Input state with the input value ignored. Ports or others: Used as ports or I/O pins for on-chip peripheral modules, and are not used as the data bus.
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Section 6 Bus Controller (BSC)
6.5.3
Basic Operation Timing
8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used in the H8S/2144B. Wait cycles cannot be inserted.
Bus cycle T1
T2
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 (D7 to D0 in H8S/2134B) D7 to D0 (Invalid in H8S/2134B)
Read
Valid
Invalid
HWR
Write D15 to D8 (D7 to D0 in H8S/2134B) Valid
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space
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Section 6 Bus Controller (BSC)
8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used in the H8S/2144B. Wait cycles can be inserted.
Bus cycle T1
T2
T3
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8 (D7 to D0 in H8S/2134B) D7 to D0 (Invalid in H8S/2134B)
Read
Valid
Invalid
HWR Write D15 to D8 (D7 to D0 in H8S/2134B)
Valid
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
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Section 6 Bus Controller (BSC)
16-Bit, 2-State Access Space [Available for H8S/2144B]: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used for even addresses, and the lower byte (D7 to D0) for odd addresses. Wait cycles cannot be inserted.
Bus cycle T1
T2
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
Write
High level
D15 to D8
Valid
D7 to D0
Undefined
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR
Write
D15 to D8
Undefined
D7 to D0
Valid
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
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Section 6 Bus Controller (BSC)
16-Bit, 3-State Access Space [Available for H8S/2144B]: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used for even addresses, and the lower byte (D7 to D0) for odd addresses. Wait cycles can be inserted.
Bus cycle T1
T2
T3
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR High level
LWR Write D15 to D8
Valid
D7 to D0
Undefined
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
T3
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High level
LWR Write D15 to D8 Undefined
D7 to D0
Valid
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle T1
T2
T3
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR Write D15 to D8 Valid
D7 to D0
Valid
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
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Section 6 Bus Controller (BSC)
6.5.4
Wait Control
When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait cycles (TW). There are three ways of inserting wait cycles: Program wait insertion, pin wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin. Program Wait Mode: A specified number of wait cycles TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits in WSCR. Pin Wait Mode: A specified number of wait cycles TW can be inserted automatically between the T2 state and T3 state when accessing the external address space always according to the settings of the WC1 and WC0 bits. If the WAIT pin is low at the falling edge of in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states to be inserted for each external device. Pin Auto-Wait Mode: A specified number of wait cycles TW can be inserted automatically between the T2 state and T3 state when accessing the external address space according to the settings of the WC1 and WC0 bits if the WAIT pin is low at the falling edge of in the last T2 state. Even if the WAIT pin is held low, TW states can be inserted only up to the specified number of cycles. This function enables the low-speed memory interface only by inputting the chip select signal to the WAIT pin. Figure 6.13 shows an example of wait cycle insertion timing in pin wait mode. The settings after a reset are: 3-state access, 3 program wait insertion, and WAIT pin input disabled.
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Section 6 Bus Controller (BSC)
By program wait T1
T2 TW
By WAIT pin
TW
TW
T3
WAIT
Address bus
AS/IOS (IOSE = 0)
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Note: shown in clock indicates the WAIT pin sampling timing.
Figure 6.13 Example of Wait Cycle Insertion Timing (Pin Wait Mode)
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Section 6 Bus Controller (BSC)
6.6
Burst ROM Interface
In this LSI, the external address space can be designated as the burst ROM space by setting the BRSTRM bit in BCR to 1, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. One or two cycles can be selected for burst ROM access. 6.6.1 Basic Operation Timing
The number of access cycles in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR. When the AST bit is set to 1, wait cycles can be inserted. One or two cycles can be selected for burst access according to the setting of the BRSTS1 bit in BCR. Wait cycles cannot be inserted in a burst cycle. Burst accesses of a maximum four words is performed when the BRSTS0 bit in BCR is cleared to 0, and burst accesses of a maximum eight words is performed when the BRSTS0 bit in BCR is set to 1. The basic access timing for the burst ROM space is shown in figures 6.14 and 6.15.
Full access Burst access
T1
T2
T3
T1
T2
T1
T2
Address bus
Only lower address changes
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read data
Read data
Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1)
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Section 6 Bus Controller (BSC)
Full access T1
T2
Burst access T1 T1
Address bus
Only lower address changes
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read data Read data
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.4, Wait Control. Wait cycles cannot be inserted in a burst cycle.
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Section 6 Bus Controller (BSC)
6.7
Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces. If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.16 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.16 (a), with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In figure 6.16 (b), an idle cycle is inserted, thus preventing data collision.
Bus cycle A
Bus cycle B
Bus cycle A Bus cycle B TI T1 T2
T1
T2
T3
T1
T2
T1
T2
T3
Address bus
RD HWR, LWR
Address bus
RD HWR, LWR Data bus
Data bus
Data collision Long output floating time
(a) No idle cycle insertion
(b) Idle cycle insertion
Figure 6.16 Examples of Idle Cycle Operation Table 6.6 shows the pin states in an idle cycle.
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Section 6 Bus Controller (BSC)
Table 6.6
Pin States in Idle Cycle
A15 to A0, IOS D7 to D0 AS RD WR
Pins (H8S/2144B) Pins (H8S/2134B) Pin State A23 to A0, IOS D15 to D0 AS RD HWR, LWR Contents of immediately following bus cycle High impedance High High High
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Section 7 I/O Ports
Section 7 I/O Ports
7.1 Overview
In the H8S/2144B, ten I/O ports (ports 1 to 6, 8, 9, A, and B) and one input-only port (port 7) are included. In the H8S/2134B, eight I/O ports (ports 1 to 6, 8, and 9) and one input-only port (port 7) are included. Table 7.1 is a summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, 6, A, and B have an on-chip input pull-up MOS function. For ports A and B, the on/off status of the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have an input pull-up MOS control register (PCR), in addition to DDR and DR, to control the on/off status of the input pull-up MOS. Ports 1 to 6, 8, 9, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, 2, and 3 can drive an LED (10 mA sink current). Port A input and output use by the VccB power supply, which is independent of the VCC power supply. When the VccB voltage is 5V, the pins on port A will be 5-V tolerant. PA4 to PA7 of port A have the capability to drive bus buffers.
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Section 7 I/O Ports
Table 7.1
Port Functions of H8S/2144B
Mode 2 Mode 3 (EXPE = 0) P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 On-chip input pullup MOSs On-chip input pullup MOSs I/O Status On-chip input pullup MOSs
Port Port 1
Description
Mode 1
(EXPE = 1) A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 A15/P27 A14/P26 A13/P25 A12/P24 A11/P23 A10/P22 A9/P21 A8/P20
General I/O port also A7 functioning as A6 address output pin A5 A4 A3 A2 A1 A0
Port 2
General I/O port also A15 functioning as A14 address output pin A13 A12 A11 A10 A9 A8
Port 3
General I/O port also D15 functioning as data D14 bus input/output pin D13 D12 D11 D10 D9 D8
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Section 7 I/O Ports
Mode 2 Port Port 4 Description General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, SCI_2 input/output, and IrDA interface input/output pins Mode 1 P47/PWX1 P46/ PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD Port 5 General I/O port also P52/SCK0 functioning as SCI_0 P51/RxD0 input/output pins P50/TxD0 General I/O port also functioning as interrupt input, FRT input/output, TMR_Y input/output, keysense interrupt input, and extended A/D input pins P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTCI/CIN0/KIN0 Port 7 General input port also functioning as A/D converter analog input and D/A converter analog output pins P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 (EXPE = 1)
Mode 3 (EXPE = 0) I/O Status
Port 6
On-chip input pullup MOSs
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Section 7 I/O Ports
Mode 2 Port Port 8 Description General I/O port also functioning as interrupt input and SCI_1 input/output pins Mode 1 (EXPE = 1)
Mode 3 (EXPE = 0) I/O Status
P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80
Port 9
General I/O port also functioning as extended data bus control input/output, subclock input, output, interrupt input, and A/D converter external trigger input pins
P97/WAIT P96//EXCL AS/IOS HWR RD P92/IRQ0 P91/IRQ1 P90/LWR/IRQ2/ADTRG PA7/KIN15/ CIN15 PA6/KIN14/ CIN14 PA5/KIN13/ CIN13 PA4/KIN12/ CIN12 PA3/KIN11/ CIN11 PA2/KIN10/ CIN10 PA1/KIN9/ CIN9 PA0/KIN8/ CIN8 PA7/A23/KIN15/ CIN15 PA6/A22/KIN14/ CIN14 PA5/A21/KIN13/ CIN13 PA4/A20/KIN12/ CIN12 PA3/A19/KIN11/ CIN11 PA2/A18/KIN10/ CIN10 PA1/A17/KIN9/ CIN9 PA0/A16/KIN8/ CIN8
P97 P96//EXCL P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG PA7/KIN15/CIN15 PA6/KIN14/CIN14 PA5/KIN13/CIN13 PA4/KIN12/CIN12 PA3/KIN11/CIN11 PA2/KIN10/CIN10 PA1/KIN9/CIN9 PA0/KIN8/CIN8 On-chip input pullup MOSs
Port A General I/O port also functioning as address output, keysense interrupt input, and extended A/D input pins
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Section 7 I/O Ports
Mode 2 Port Description Mode 1 (EXPE = 1)
Mode 3 (EXPE = 0) PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 I/O Status On-chip input pullup MOSs
Port B General I/O port also PB7/D7 functioning as data PB6/D6 bus input/output pins PB5/D5 PB4/D4 PB3/D3 PB2/D2 PB1/D1 PB0/D0
Table 7.2
Port Functions of H8S/2134B
Mode 2 Mode 3 (EXPE = 0) P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 On-chip input pullup MOSs I/O Status On-chip input pullup MOSs
Port Port 1
Description
Mode 1
(EXPE = 1) A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 A15/P27 A14/P26 A13/P25 A12/P24 A11/P23 A10/P22 A9/P21 A8/P20
General I/O port also A7 functioning as A6 address output pin A5 A4 A3 A2 A1 A0
Port 2
General I/O port also A15 functioning as A14 address output pin A13 A12 A11 A10 A9 A8
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Section 7 I/O Ports
Mode 2 Port Port 3 Description Mode 1 (EXPE = 1)
Mode 3 (EXPE = 0) P37 P36 P35 P34 P33 P32 P31 P30 I/O Status On-chip input pullup MOSs
General I/O port also D7 functioning as data D6 bus input/output pin D5 D4 D3 D2 D1 D0
Port 4
General I/O port also functioning as PWMX output, TMR_0 and TMR_1 input/output, SCI_2 input/output, and IrDA interface input/output pins
P47/PWX1 P46/ PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/TMRI0/SCK2 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD
Port 5
General I/O port also P52/SCK0 functioning as SCI_0 P51/RxD0 input/output pins P50/TxD0 General I/O port also functioning as interrupt input, FRT input/output, TMR_Y input/output, keysense interrupt input, and extended A/D input pins P67/CIN7/KIN7/IRQ7 P66/FTOB/CIN6/KIN6/IRQ6 P65/FTID/CIN5/KIN5 P64/FTIC/CIN4/KIN4 P63/FTIB/CIN3/KIN3 P62/FTIA/CIN2/KIN2/TMIY P61/FTOA/CIN1/KIN1 P60/FTC/CIN0/KIN0 On-chip input pullup MOSs
Port 6
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Section 7 I/O Ports
Mode 2 Port Port 7 Description General input port also functioning as A/D converter analog input and D/A converter analog output pins Mode 1 P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Port 8 General I/O port also functioning as interrupt input and SCI_1 input/output pins P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80 Port 9 General I/O port also functioning as extended data bus control input/output, subclock input, output, interrupt input, and A/D converter external trigger input pins P97/WAIT P96//EXCL AS/IOS WR RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG (EXPE = 1)
Mode 3 (EXPE = 0) I/O Status
P97 P96//EXCL P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG
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Section 7 I/O Ports
7.2
Port 1
Port 1 is an 8-bit I/O port. Port 1 pins also function as address output pins. Port 1 functions change according to the operating mode. Port 1 has an on-chip input pull-up MOS function that can be controlled by software. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) 7.2.1 Port 1 Data Direction Register (P1DDR)
P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In mode 1: Each pin of port 1 is address output regardless of the set value of P1DDR. In modes 2 and 3 (EXPE=1): The corresponding port 1 pins are address output ports when P1DDR bits are set to 1, and input ports when cleared to 0. In modes 2 and 3 (EXPE=0): The corresponding port 1 pins are output ports when the P1DDR bits are set to 1, and input ports when cleared to 0.
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Section 7 I/O Ports
7.2.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read.
7.2.3
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the on/off status of the port 1 on-chip input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1.
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7.2.4
Pin Functions
* P17/A7, P16/A6, P15/A5, P14/A4, P13/A3, P12/A2, P11/A1, and P10/A0 Pin functions are switched as shown below according to the combination of the P1nDDR bit and operating mode.
Operating Mode P1nDDR Pin Function [Legend] n = 7 to 0 Mode 1 -- A7 to A0 output pins Mode 2, 3 (EXPE = 1) 0 P17 to P10 input pins 1 A7 to A0 output pins Mode 2, 3 (EXPE = 0) 0 P17 to P10 input pins 1 P17 to P10 output pins
7.2.5
Port 1 Input Pull-Up MOS
Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.3 summarizes the input pull-up MOS states. Table 7.3
Mode 1 2, 3
Input Pull-Up MOS States (Port 1)
Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off
[Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P1DDR = 0, and P1PCR = 1; otherwise off.
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Section 7 I/O Ports
7.3
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output pins. Port 2 functions change according to the operating mode. Port 2 has an on-chip input pull-up MOS function that can be controlled by software. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) 7.3.1 Port 2 Data Direction Register (P2DDR)
P2DDR specifies input or output for the pins of port 2 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In Mode 1: The corresponding port 2 pins are address outputs, regardless of the P2DDR setting. Modes 2 and 3 (EXPE = 1): The corresponding port 2 pins are address outputs when P2DDR bits are set to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to 1. To ensure normal accesses to an external space, port 2 pins should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. Modes 2 and 3 (EXPE = 0): The corresponding port 2 pins are output ports when P2DDR bits are set to 1, and input ports when cleared to 0.
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Section 7 I/O Ports
7.3.2
Port 2 Data Register (P2DR)
P2DR stores output data for port 2.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read.
7.3.3
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 on-chip input pull-up MOSs.
Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 2 and 3, the input pull-up MOS is turned on when a P2PCR bit is set to 1 in the input port state.
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7.3.4
Pin Functions
To ensure normal access to external space, P27 should not be set as an on-chip peripheral module output pin when port 2 pins are used as address output pins. * P27/A15, P26/A14, P25/A13, and P24/A12 Pin functions are switched as shown below according to the combination of the IOSE bit in SYSCR, P27DDR bit, and operating mode.
Operating Mode P2nDDR IOSE Pin Function Mode 1 -- -- A15 to A12 output pins 0 -- P27 to P24 input pins 0 A15 to A12 output pins Mode 2, 3 (EXPE = 1) 1 1 P27 to P24 input pins Mode 2, 3 (EXPE = 0) 0 -- P27 to P24 input pins 1 -- P27 to P24 input pins
[Legend] n = 7 to 4
* P23/A11, P22/A10, P21/A9, and P20/A8 Pin functions are switched as shown below according to the combination of the P2nDDR bit and operating mode.
Operating Mode P2nDDR Pin Function Mode 1 -- A11 to A8 output pins Mode 2, 3 (EXPE = 1) 0 P23 to P20 input pins 1 A11 to A8 output pins Mode 2, 3 (EXPE = 0) 0 P23 to P20 input pins 1 P23 to P20 input pins
[Legend] n = 3 to 0
7.3.5
Port 2 Input Pull-Up MOS
Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.4 summarizes the input pull-up MOS states.
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Section 7 I/O Ports
Table 7.4
Mode 1 2, 3
Input Pull-Up MOS States (Port 2)
Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off
[Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P2DDR = 0, and P2PCR = 1; otherwise off.
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Section 7 I/O Ports
7.4
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus. Port 3 functions change according to the operating mode. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) 7.4.1 Port 3 Data Direction Register (P3DDR)
P3DDR specifies input or output for the pins of port 3 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Modes 1, 2, and 3 (EXPE = 1) The input/output direction specified by P3DDR is ignored, and pins automatically function as data I/O pins. Modes 2 and 3 (EXPE = 0) The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when cleared to 0.
7.4.2
Port 3 Data Register (P3DR)
P3DR stores output data of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read.
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7.4.3
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 2 and 3 (when EXPE = 0), the input pullup MOS is turned on when a P3PCR bit is set to 1 in the input port state. The input pull-up MOS function cannot be used when the host interface is enabled.
7.4.4
Pin Functions
* P37/D15*, P36/D14*, P35/D13*, P34/D12*, P33/D11*, P32/D10*, P31/D9*, and P30/D8* Pin functions are switched as shown below according to the combination of the P3nDDR bit and operating mode.
Operating Mode Mode 1, 2, 3 (EXPE = 1) P3nDDR Pin Function Note: -- D15 to D8* input/output pins 0 P37 to P30 input pins Mode 2, 3 (EXPE = 0) 1 P37 to P30 output pins
n = 7 to 0 * D7 to D0 in the H8S/2134B are equivalent of D15 to D8 in the H8S/2144B.
7.4.5
Port 3 Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.5 summarizes the input pull-up MOS states.
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Section 7 I/O Ports
Table 7.5
Mode
Input Pull-Up MOS States (Port 3)
Reset Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off
1, 2, 3 (EXPE = 1) Off 2, 3 (EXPE = 0)
[Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P3DDR = 0, and P3PCR = 1; otherwise off.
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Section 7 I/O Ports
7.5
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins also function as PWMX output pins, TMR_0 and TMR_1 I/O pins, SCI_2 I/O pins, and IrDA interface I/O pins. Port 4 pin functions are the same in all operating modes. Port 4 has the following registers. * Port 4 data direction register (P4DDR) * Port 4 data register (P4DR) 7.5.1 Port 4 Data Direction Register (P4DDR)
P4DDR specifies input or output for the pins of port 4 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. As 14-bit PWM and SCI_2 are initialized in software standby mode, the pin states are determined by the TMR_0, TMR_1, P4DDR, and P4DR specifications.
7.5.2
Port 4 Data Register (P4DR)
P4DR stores output data for port 4.
Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly, regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0, the pin states are read.
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7.5.3
Pin Functions
* P47/PWX1 Pin functions are switched as shown below according to the combination of the OEB bit in DACR of the 14-bit PWM and the P47DDR bit.
OEB P47DDR Pin Function 0 P47 input pin 0 1 P47 output pin 1 -- PWX1 output pin
* P46/PWX0 Pin functions are switched as shown below according to the combination of the OEA bit in DACR of the 14-bit PWM and the P46DDR bit.
OEA P46DDR Pin Function 0 P46 input pin 0 1 P46 output pin 1 -- PWX0 output pin
* P45/TMRI1 Pin functions are switched as shown below according to the P45DDR bit.
P45DDR Pin Function Note: * 0 P45 input pin TMRI1 input pin* When bits CCLR1 and CCLR0 in TCR1 of TMR_1 are set to 1, this pin is used as the TMRI1 input pin. 1 P45 output pin
* P44/TMO1 Pin functions are switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_1 and the P44DDR bit.
OS3 to OS0 P44DDR Pin Function 0 P44 input pin All 0 1 P44 output pin Not all 0 -- TMO1 output pin
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Section 7 I/O Ports
* P43/TMCI1 Pin functions are switched as shown below according to the P43DDR bit.
P43DDR Pin Function Note: * 0 P43 input pin TMCI1 input pin* When the external clock is selected by bits CKS2 to CKS0 in TCR1 of TMR_1, this pin is used as the TMCI1 input pin. 1 P43 output pin
* P42/TMRI0/SCK2 Pin functions are switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_2, the C/A bit in SMR of SCI_2, and the P42DDR bit.
CKE1 C/A CKE0 P42DDR Pin Function Note: * 0 P42 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- --
P42 output pin SCK2 output pin SCK2 output pin SCK2 input pin TMRI0 input pin*
When bits CCLR1 and CCLR0 in TCR0 of TMR_0 are set to 1, this pin is used as the TMRI0 input pin.
* P41/TMO0/RxD2/IrRxD Pin functions are switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR0, the RE bit in SCR of SCI_2 and the P41DDR bit.
OS3 to OS0 RE P41DDR Pin Function Note: * 0 P41 input pin 0 1 P41 output pin All 0 1 -- RxD2/IrRxD input pin Not all 0 0 -- TMO0 output pin
When this pin is used as the TMO0 output pin, bit RE in SCR of SCI_2 must be cleared to 0.
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* P40/TMCI0/TxD2/IrTxD Pin functions are switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P40DDR bit.
TE P40DDR Pin Function 0 P40 input pin 0 1 P40 output pin TMCI0 input pin* Note: * When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR_0, this pin is used as the TMCI0 input pin. 1 -- TxD2/IrTxD output pin
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Section 7 I/O Ports
7.6
Port 5
Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_0 I/O pins. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) 7.6.1 Port 5 Data Direction Register (P5DDR)
P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis.
Bit 7 to 3 2 1 0 Bit Name -- Initial Value All 1 R/W -- Description Reserved The initial value must not be changed. P52DDR P51DDR P50DDR 0 0 0 W W W The corresponding port 5 pins are output ports when P5DDR bits are set to 1, and input ports when cleared to 0. As SCI_0 is initialized in software standby mode, the pin states are determined by the P5DDR and P5DR specifications.
7.6.2
Port 5 Data Register (P5DR) P3PCR
P5DR stores output data for port 5 pins.
Bit 7 to 3 2 1 0 Bit Name -- Initial Value All 1 R/W -- Description Reserved The initial value must not be changed. P52DR P51DR P50DR 0 0 0 R/W R/W R/W If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly, regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read.
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7.6.3
Pin Functions
* P52/SCK0 Pin functions are switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_0, the C/A bit in SMR of SCI_0, the ICE bit in ICCR of IIC_0, and the P52DDR bit.
CKE1 C/A CKE0 P52DDR Pin Function 0 P52 input pin 0 1 P52 output pin 0 1 -- SCK0 output pin 0 1 -- -- SCK0 output pin 1 -- -- -- SCK0 input pin
* P51/RxD0 Pin functions are switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P51DDR bit.
RE P51DDR Pin Function 0 P51 input pin 0 1 P51 output pin 1 -- RxD0 input pin
* P50/TxD0 Pin functions are switched as shown below according to the combination of the TE bit in SCR of SCI_0 and the P50DDR bit.
TE P50DDR Pin Function 0 P50 input pin 0 1 P50 output pin 1 -- TxD0 output pin
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Section 7 I/O Ports
7.7
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT I/O pins, the TMR_Y input pin, key-sense interrupt input pins, extended A/D converter input pins, and external interrupt input pins. The port 6 input level can be switched in four stages. Port 6 pin functions are the same in all operating modes. Port 6 has the following registers. * * * * Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Port 6 pull-up MOS control register (KMPCR6) System control register 2 (SYSCR2) Port 6 Data Direction Register (P6DDR)
7.7.1
P6DDR specifies input or output for the pins of port 6 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 6 pins are output ports when P6DDR bits are set to 1, and input ports when cleared to 0.
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Section 7 I/O Ports
7.7.2
Port 6 Data Register (P6DR)
P6DR stores output data for port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read.
7.7.3
Port 6 Pull-Up MOS Control Register (KMPCR)
KMPCR controls the port 6 on-chip input pull-up MOSs on a bit-by-bit basis. To make the settings of this register valid, clear bit MSTP2 in MSTPCRL to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The input pull-up MOS is turned on when a KMPCR bit is set to 1 while the corresponding P6DDR bit is cleared to 0 (input port setting).
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Section 7 I/O Ports
7.7.4
System Control Register 2 (SYSCR2)
SYSCR2 controls the signal levels input on port 6 and current specifications.
Bit 7 6 Bit Name KWUL1 KWUL0 Initial Value 0 0 R/W R/W R/W Description Key Wakeup Level 1 and 0 Selects the input level of port 6. The input levels of other functions of the multiplexed pin are also decided by these bits. 00: Normal input level 01: Input level 1 10: Input level 2 11: Input level 3 5 P6PUE 0 R/W Port 6 Input Pull-Up MOS Extra Selects the specification of the input pull-up MOS in current driving ability. 0: Normal current specification 1: Limited current specification 4 3 to 0 -- -- 0 All 0 -- R/W Reserved Do not write 1 to this bit. Reserved Do not write 1 to this bit
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Section 7 I/O Ports
7.7.5
Pin Functions
* P67/CIN7/KIN7/IRQ7 Pin functions are switched as shown below according to the P67DDR bit.
P67DDR Pin Function Note: * 0 P67 input pin 1 P67 output pin
IRQ7 input pin, KIN7 input pin, CIN7 input pin* This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER. It can always be used as the KIN7 or CIN7 input pin.
* P66/FTOB/CIN6/KIN6/IRQ6 Pin functions are switched as shown below according to the combination of the OEB bit in TOCR of the FRT and the P66DDR bit.
OEB P66DDR Pin Function Note: * 0 0 P66 input pin 1 P66 output pin IRQ6 input pin, KIN6 input pin, CIN6 input pin* This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the KMIMR6 bit in KMIMR is 0. It can always be used as the KIN6 or CIN6 input pin. 1 -- FTOB output pin
* P65/FTID/CIN5/KIN5
P65DDR Pin Function Note: * 0 P65 input pin 1 P65 output pin
FTID input pin, KIN5 input pin, CIN5 input pin* This pin can always be used as the FTID, KIN5, or CIN5 input pin.
* P64/FTIC/CIN4/KIN4 Pin functions are switched as shown below according to the P64DDR bit.
P64DDR Pin Function Note: * 0 P64 input pin 1 P64 output pin
FTIC input pin, KIN4 input pin, CIN4 input pin* This pin can always be used as the FTIC, KIN4, or CIN4 input pin.
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Section 7 I/O Ports
* P63/FTIB/CIN3/KIN3
P63DDR Pin Function Note: * 0 P63 input pin 1 P63 output pin
FTIB input pin, KIN3 input pin, CIN3 input pin* This pin can always be used as the FTIB, KIN3, or CIN3 input pin.
* P62/FTIA/CIN2/KIN2/TMIY
P62DDR Pin Function Note: * 0 P62 input pin 1 P62 output pin
FTIA input pin, TMIY input pin, KIN2 input pin, CIN2 input pin* This pin can always be used as the FTIA, TMIY, KIN2, or CIN2 input pin.
* P61/FTOA/CIN1/KIN1 Pin functions are switched as shown below according to the combination of the OEA bit in TOCR of the FRT and the P61DDR bit.
OEA P61DDR Pin Function Note: * 0 0 P61 input pin 1 P61 output pin KIN1 input pin, CIN1 input pin* This pin can always be used as the KIN1 or CIN1 input pin. 1 -- FTOA output pin
* P60/FTCI/CIN0/KIN0
P60DDR Pin Function Note: * 0 P60 input pin 1 P60 output pin
FTCI input pin, KIN0 input pin, CIN0 input pin* This pin is used as the FTCI input pin when an external clock is selected with bits CKS1 and CKS0 in TCR of the FRT. It can always be used as the KIN0 or CIN0 input pin.
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Section 7 I/O Ports
7.7.6
Port 6 Input Pull-Up MOS
Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS current specification can be changed by means of the P6PUE bit. When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is always off. Table 7.6 summarizes the input pull-up MOS states. Table 7.6
Mode 1, 2, 3
Input Pull-Up MOS States (Port 6)
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, P6DDR = 0, and KMPCR = 1; otherwise off.
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Section 7 I/O Ports
7.8
Port 7
Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins and D/A converter analog output pins. Port 7 functions are the same in all operating modes. Port 7 has the following register. * Port 7 input data register (P7PIN) 7.8.1 Port 7 Input Data Register (P7PIN)
P7PIN reflects the pin states of port 7.
Bit 7 6 5 4 3 2 1 0 Note: * Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a P7PIN read is performed, the pin states are always read. P7PIN has the same address as PBDDR; if a write is performed, data will be written into PBDDR and the port B setting will be changed.
Determined by the pin states of P77 to P70.
7.8.2
Pin Functions
* P77/AN7/DA1 Pin functions are switched as shown below according to the combination of the DAE bit in DACR of the D/A converter and the DAOE1 bit.
DAOE1 DAE Pin Function Note: * 0 P77 input pin 0 1 DA1 input pin AN7 input pin* This pin can always be used as the AN7 input pin. 1 -- DA1 output pin
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Section 7 I/O Ports
* P76/AN6/DA0 Pin functions are switched as shown below according to the combination of the DAE bit in DACR of the D/A converter and the DAOE0 bit.
DAOE0 DAE Pin Function Note: * 0 P76 input pin 0 1 DA0 output pin AN6 input pin* This pin can always be used as the AN6 input pin. 1 -- DA0 output pin
* P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0
Pin Function Note: * P75 to P70 input pins AN5 to AN0 input pin* This pin can always be used as the AN5 to AN0 input pins.
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Section 7 I/O Ports
7.9
Port 8
Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins and interrupt input pins. Port 8 pin functions are the same in all operating modes. Port 8 has the following registers. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) 7.9.1 Port 8 Data Direction Register (P8DDR)
P8DDR specifies input or output for the pins of port 8 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name -- P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value 1 0 0 0 0 0 0 0 R/W -- W W W W W W W Description Reserved The initial value must not be changed. P8DDR has the same address as PBPIN, and if read, the port B state will be returned. (Available only in the H8S/2144B.) The corresponding port 8 pins are output ports when P8DDR bits are set to 1, and input ports when cleared to 0.
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Section 7 I/O Ports
7.9.2
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins (P86 to P80).
Bit 7 6 5 4 3 2 1 0 Bit Name -- P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial Value 1 0 0 0 0 0 0 0 R/W -- R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value must not be changed. If a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly, regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0, the pin states are read.
7.9.3
Pin Functions
* P86/IRQ5/ SCK1 Pin functions are switched as shown below according to the combination of the CKE1 and CKE0 bits in SCR of SCI_1, the C/A bit in SMR of SCI_1, and the P86DDR bit.
CKE1 C/A CKE0 P86DDR Pin Function 0 P86 input pin 0 1 P86 output pin 0 1 -- SCK1 output pin IRQ5 input pin* Note: * When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. 0 1 -- -- SCK1 output pin 1 -- -- -- SCK1 input pin
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Section 7 I/O Ports
* P85/IRQ4/RxD1 Pin functions are switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P85DDR bit.
RE P85DDR Pin Function Note: * 0 P85 input pin 0 1 P85 output pin IRQ4 input pin* When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin. 1 -- RxD1 input pin
* P84/IRQ3/TxD1 Pin functions are switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P84DDR bit.
TE P84DDR Pin Function Note: * 0 P84 input pin 0 1 P84 output pin IRQ3 input pin* When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin. 1 -- TxD1 output pin
* P83 Pin functions are switched as shown below according to the P83DDR bit.
P83DDR Pin Function 0 P83 input pin 1 P83 output pin
* P82 Pin functions are switched as shown below according to the P82DDR bit.
P82DDR Pin Function 0 P82 input pin 1 P82 output pin
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Section 7 I/O Ports
* P81 Pin functions are switched as shown below according to the P81DDR bit.
P81DDR Pin Function 0 P81 input pin 1 P81 output pin
* P80 Pin functions are switched as shown below according to the P80DDR bit.
P80DDR Pin Function 0 P80 input pin 1 P80 output pin
7.10
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins, the A/D converter input pin, the subclock input pin, bus control signal I/O pins, and the system clock () output pin. Port 9 has the following registers. * Port 9 data direction register (P9DDR) * Port 9 data register (P9DR)
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7.10.1
Port 9 Data Direction Register (P9DDR)
P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Initial Value 0 1/0* 0 0 0 0 0 0 R/W W W W W W W W W Description P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3). Modes 1, 2, and 3 (EXPE = 1): Pin P97 functions as a bus control input (WAIT) or an I/O port according to the wait mode setting. When P97 functions as an I/O port, it becomes an output port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0. Pin P96 functions as the output pin when P96DDR is set to 1, and as the subclock input (EXCL) or an input port when P96DDR is cleared to 0. Pins P95 to P93 automatically become bus control outputs (AS/IOS, HWR, WR, RD), regardless of the input/output direction indicated by P95DDR to P93DDR. Pins P92 and P91 become output ports when P92DDR and P91DDR are set to 1, and input ports when P92DDR and P91DDR are cleared to 0. When the ABW bit in WSCR is cleared to 0 (clearing to 0 is prohibited in the H8S/2134B), pin P90 becomes a bus control output (LWR), regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90 becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0. Modes 2 and 3 (EXPE = 0): When the corresponding P9DDR bits are set to 1, pin P96 functions as the output pin and pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the corresponding pins become input ports. Note: * The initial value of P96DDR is 1 (mode 1) or 0 (modes 2 and 3).
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Section 7 I/O Ports
7.10.2
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR * Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR values are read directly, regardless of the actual pin states. If a port 9 read is performed while P9DDR bits are cleared to 0, the pin states are read. For P96, the pin state is always read.
The initial value of bit 6 is determined according to the P96 pin state.
7.10.3
Pin Functions
* P97/WAIT Pin functions are switched as shown below according to the combination of operating mode, the WMS1 bit in WSCR, and the P97DDR bit.
Operating Mode WMS1 P97DDR Pin Function 0 P97 input pin Modes 1, 2, 3 (EXPE = 1) 0 1 P97 output pin 1 -- WAIT input pin 0 P97 input pin Modes 2, 3 (EXPE = 0) -- 1 P97 output pin
* P96//EXCL Pin functions are switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit.
P96DDR EXCLE Pin Function Note: * 0 P96 input pin 0 1 EXCL input pin 1 0 output pin
When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.
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* P95/AS/IOS Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the P95DDR bit.
Operating Mode P95DDR IOSE Pin Function 0 AS output pin Modes 1, 2, 3 (EXPE = 1) -- 1 IOS output pin Modes 2, 3 (EXPE = 0) 0 -- P95 input pin 1 -- P95 output pin
* P94/HWR* Pin functions are switched as shown below according to the combination of operating mode and the P94DDR bit.
Operating Mode P94DDR Pin Function Note: * Modes 1, 2, 3 (EXPE = 1) -- HWR* output pin The WR pin in the H8S/2134B 0 P94 input pin Modes 2, 3 (EXPE = 0) 1 P94 output pin
* P93/RD Pin functions are switched as shown below according to the combination of operating mode and the P93DDR bit.
Operating Mode P93DDR Pin Function Modes 1, 2, 3 (EXPE = 1) -- RD output pin 0 P93 input pin Modes 2, 3 (EXPE = 0) 1 P93 output pin
* P92/IRQ0
P92DDR Pin Function Note: * 0 P92 input pin IRQ0 input pin* When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. 1 P92 output pin
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* P91/IRQ1
P91DDR Pin Function Note: * 0 P91 input pin IRQ1 input pin* When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin. 1 P91 output pin
* P90/LWR*2/IRQ2/ADTRG Pin functions are switched as shown below according to the combination of operating mode, the ABW bit in WSCR, and the P90DDR bit.
Operating Mode ABW P90DDR Pin Function Note: 0 -- LWR* output pin
2
Modes 1, 2, 3 (EXPE = 1) 1 0 P90 input pin 1 P90 output pin
Modes 2, 3 (EXPE = 0) -- 0 P90 input pin
1
1 P90 output pin
IRQ2 input pin, ADTRG input pin*
1. When the ABW bit in WSCR is set to 1 in mode 1, 2, or 3 (EXPE = 1), or the IRQ2E bit in IER is set to 1 in mode 2 or 3 (EXPE = 0), this pin is used as the IRQ2 input pin. When TRGS1 and TRGS0 in ADCR of the A/D converter are both set to 1, this pin is used as the ADTRG input pin. 2. The LWR pin is not available in the H8S/2134B. Do not clear the ABW bit in WSCR to 0.
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Section 7 I/O Ports
7.11
Port A (Only for H8S/2144B)
Port A is an 8-bit I/O port. Port A pins also function as key-sense interrupt input pins, extended A/D converter input pins, and address output pins. Port A pin functions change according to the operating mode. Port A input/output operates by VccB power independent from the Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the following registers. PADDR and PAPIN have the same address. * Port A data direction register (PADDR) * Port A output data register (PAODR) * Port A input data register (PAPIN) 7.11.1 Port A Data Direction Register (PADDR)
PADDR specifies input or output for the pins of port A on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In mode 1, 2 (EXPE = 0), or 3: The corresponding port A pins are output ports when PADDR bits are set to 1, and input ports when cleared to 0. In mode 2 (EXPE = 1): The corresponding port A pins are address output when PADDR bits are set to 1, and input ports when cleared to 0. The port A pins changes from the address I/O ports to output ports by setting the IOSE bit to 1. PADDR has the same address as PAPIN, if read, port A status is returned.
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Section 7 I/O Ports
7.11.2
Port A Output Data Register (PAODR)
PAODR stores output data for port A.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PAODR can always be read or written to, regardless of the contents of PADDR.
7.11.3
Port A Input Data Register (PAPIN)
PAPIN indicates the port A state.
Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Reading PAPIN always returns the pin states. PAPIN has the same address as PADDR. If a write is performed, the port A settings will change.
The initial value is determined according to the PA7 to PA0 pin states.
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7.11.4
Pin Functions
* PA7/A23/KIN15/CIN15 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the PA7DDR bit.
Operating Mode PA7DDR IOSE Pin Function Modes 1, 2 (EXPE = 0), 3 0 -- PA7 input pin 1 -- PA7 output pin 0 -- PA7 input pin Mode 2 (EXPE = 1) 1 0 A23 output pin 1 PA7 output pin
KIN15 input pin, CIN15 input pin* Note: * When the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the KIN15 or CIN15 input pin.
* PA6/A22/KIN14/CIN14 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the PA6DDR bit.
Operating Mode PA6DDR IOSE Pin Function Note: * Modes 1, 2 (EXPE = 0), 3 0 -- PA6 input pin 1 -- PA6 output pin 0 -- PA6 input pin Mode 2 (EXPE = 1) 1 0 A22 output pin 1 PA6 output pin
KIN14 input pin, CIN14 input pin* When the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the KIN14 or CIN14 input pin.
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* PA5/A21/KIN13/CIN13 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the PA5DDR bit.
Operating Mode PA5DDR IOSE Pin Function Note: * Modes 1, 2 (EXPE = 0), 3 0 -- PA5 input pin 1 -- PA5 output pin 0 -- PA5 input pin Mode 2 (EXPE = 1) 1 0 A21 output pin 1 PA5 output pin
KIN13 input pin, CIN13 input pin* When the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the KIN13, or CIN13 input pin.
* PA4/A20/KIN12/CIN12 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the PA4DDR bit.
Operating Mode PA4DDR IOSE Pin Function Note: * Modes 1, 2 (EXPE = 0), 3 0 -- PA4 input pin 1 -- PA4 output pin 0 -- PA4 input pin Mode 2 (EXPE = 1) 1 0 A20 output pin 1 PA4 output pin
KIN12 input pin, CIN12 input pin* When the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the KIN12 or CIN12 input pin.
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Section 7 I/O Ports
* PA3/A19/KIN11/CIN11 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the PA3DDR bit.
Operating Mode PA3DDR IOSE Pin Function Note: * Modes 1, 2 (EXPE = 0), 3 0 -- PA3 input pin 1 -- PA3 output pin 0 -- PA3 input pin Mode 2 (EXPE = 1) 1 0 A19 output pin 1 PA3 output pin
KIN11 input pin, CIN11 input pin* This pin can always be used as the KIN11 or CIN11 input pin.
* PA2/A18/KIN10/CIN10 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR, and the PA2DDR bit.
Operating Mode PA2DDR IOSE Pin Function Note: * Modes 1, 2 (EXPE = 0), 3 0 -- PA2 input pin 1 -- PA2 output pin 0 -- PA2 input pin Mode 2 (EXPE = 1) 1 0 A18 output pin 1 PA2 output pin
KIN10 input pin, CIN10 input pin* This pin can always be used as the KIN10 or CIN10 input pin.
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* PA1/A17/KIN9/CIN9 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and the PA1DDR bit.
Operating Mode PA1DDR IOSE Pin Function Modes 1, 2 (EXPE = 0), 3 0 -- PA1 input pin 1 -- PA1 output pin 0 -- PA1 input pin 0 A17 output pin Mode 2 (EXPE = 1) 1 1 PA1 output pin
KIN9 input pin, CIN9 input pin* Note: * This pin can always be used as the KIN9 or CIN9 input pin.
* PA0/A16/ KIN8/CIN8 Pin functions are switched as shown below according to the combination of operating mode, the IOSE bit in SYSCR and the PA0DDR bit.
Operating Mode PA0DDR IOSE Pin Function Modes 1, 2 (EXPE = 0), 3 0 -- PA0 input pin 1 -- PA0 output pin 0 -- PA0 input pin 0 A16 output pin Mode 2 (EXPE = 1) 1 1 PA0 output pin
KIN8 input pin, CIN8 input pin* Note: * This pin can always be used as the KIN8 or CIN8 input pin.
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Section 7 I/O Ports
7.11.5
Port A Input Pull-Up MOS
Port A has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. The input pull-up MOS for pins PA7 to PA4 is always off when IICS is set to 1. Table 7.7 summarizes the input pull-up MOS states. Table 7.7
Mode 1, 2, 3
Input Pull-Up MOS States (Port A)
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, PADDR = 0, and PAODR = 1; otherwise off.
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Section 7 I/O Ports
7.12
Port B (Only for H8S/2144B)
Port B is an 8-bit I/O port. Port B pins also have a data bus input/output function. The pin functions depend on the operating mode. Port B has the following registers. * Port B data direction register (PBDDR) * Port B output data register (PBODR) * Port B input data register (PBPIN) 7.12.1 Port B Data Direction Register (PBDDR)
PBDDR specifies input or output for the pins of port B on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be returned. * Modes 1, 2, and 3 (EXPE = 1) When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins (D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0. * Modes 2 and 3 (EXPE = 0) A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input port if the bit is cleared to 0.
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Section 7 I/O Ports
7.12.2
Port B Output Data Register (PBODR)
PBODR stores output data for port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PBODR can always be read or written to, regardless of the contents of PBDDR.
7.12.3
Port B Input Data Register (PBPIN)
PBPIN indicates the port B state.
Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description Reading PBPIN always returns the pin states. PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR and the port 8 settings will change.
The initial value is determined according to the PB7 to PB0 pin states.
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Section 7 I/O Ports
7.12.4
Pin Functions
* PB7/D7, PB6/D6, PB5/D5, PB4/D4, PB3/D3, PB2/D2, PB1/D1, and PB0/D0 Pin functions are switched as shown below according to the combination of the operating mode, the PBnDDR bit, and the ABW bit in WSCR.
Operating Mode ABW PBnDDR Pin Function Note: n =7 to 0 Mode 1 and Modes 2, 3 (EXPE = 1) 0 -- Dn I/O pin 0 PBn input pin 1 1 PBn output pin 0 PBn input pin Modes 2, 3 (EXPE = 0) -- 1 PBn output pin
7.12.5
Port B Input Pull-Up MOS
Port B has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. When a pin is specified as an output pin, the input pull-up MOS is always off. Table 7.8 summarizes the input pull-up MOS states. Table 7.8
Mode 1, 2, 3 (EXPE = 1) with ABW in WSCR = 0 1, 2, 3 (EXPE = 1) with ABW in WSCR = 1, or 2, 3 (EXPE = 0)
Input Pull-Up MOS States (Port B)
Reset Off Hardware Standby Mode Off Software Standby Mode Off On/Off In Other Operations Off On/Off
[Legend] Off: Input pull-up MOS is always off. On/Off: On when the pin is in the input state, PBDDR = 0, and PBODR = 1; otherwise off.
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Section 7 I/O Ports
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Section 8 14-Bit PWM Timer (PWMX)
Section 8 14-Bit PWM Timer (PWMX)
This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
8.1
Features
* Division of pulse into multiple base cycles to reduce ripple * Two resolution settings The resolution can be set equal to one or two system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Four operating speeds * Four operation clocks (by combination of two resolution settings and two base cycle settings) Figure 8.1 shows a block diagram of the PWM (D/A) module.
Internal clock /2
Internal data bus
Select clock
Clock
Base cycle compare match A
Bus interface
PWX0
Fine-adjustment pulse addition
Comparator A
Comparator B
DADRA DADRB
PWX1
Base cycle compare match B
Fine-adjustment pulse addition
Control logic Base cycle overflow
DACNT
DACR Module data bus
[Legend] DACR : PWM D/A control register DADRA : PWM D/A data register A DADRB : PWM D/A data register B DACNT : PWM D/A counter
Figure 8.1 PWM (D/A) Block Diagram
PWM1411A_010020020700
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Section 8 14-Bit PWM Timer (PWMX)
8.2
Input/Output Pins
Table 8.1 lists the PWM (D/A) module input and output pins. Table 8.1
Name PWM output pin X0 PWM output pin X1
Pin Configuration
Abbreviation I/O PWX0 PWX1 Output Output Function PWM output of PWMX channel A PWM output of PWMX channel B
8.3
Register Descriptions
The PWM (D/A) module has the following registers. The PWM (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * * * * * * * PWM (D/A) counter H (DACNTH) PWM (D/A) counter L (DACNTL) PWM (D/A) data register AH (DADRAH) PWM (D/A) data register AL (DADRAL) PWM (D/A) data register BH (DADRBH) PWM (D/A) data register BL (DADRBL) PWM (D/A) control register (DACR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. 8.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. Since DACNT consists of 16-bit data, DACNT transfers data to the CPU via the temporary register (TEMP). For details, refer to section 8.4, Bus Master Interface.
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Section 8 14-Bit PWM Timer (PWMX)
DACNTH Bit (CPU) Bit (Counter) : : 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10
DACNTL 4 11 3 12 2 13 1 0 REGS
* DACNTH
Bit 7 to 0 Bit Name UC7 to UC0 Initial Value All 0 R/W R/W Description Upper Up-Counter
* DACNTL
Bit 7 to 2 1 0 Bit Name UC8 to UC13 -- REGS Initial Value All 0 R/W R/W Description Lower Up-Counter
1 1
R R/W
Reserved This bit is always read as 1 and cannot be modified. Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed
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Section 8 14-Bit PWM Timer (PWMX)
8.3.2
PWM (D/A) Data Registers A and B (DADRA, DADRB)
DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. Since DADR consists of 16-bit data, DADR transfers data to the CPU via the temporary register (TEMP). For details, refer to section 8.4, Bus Master Interface. * DADRA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT.
Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) x 256 DADR range = H'0103 to H'FFFF
0
--
1
R
Reserved This bit is always read as 1 and cannot be modified.
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Section 8 14-Bit PWM Timer (PWMX)
* DADRB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA1 and DA0) cleared to 0. The two lowest data bits correspond to the two highest bits in DACNT.
Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DADR range = H'0401 to H'FFFD 1: Base cycle = resolution (T) x 256 DADR range = H'0103 to H'FFFF
0
REGS
1
R/W
Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed
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Section 8 14-Bit PWM Timer (PWMX)
8.3.3
PWM (D/A) Control Register (DACR)
DACR selects test mode, enables the PWM outputs, and selects the output phase and operating speed.
Bit 7 Bit Name TEST Initial Value 0 R/W R/W Description Test Mode Selects test mode, which is used in testing this LSI. Normally this bit should be cleared to 0. 0: PWM (D/A) in user state: Normal operation 1: PWM (D/A) in test state: Correct conversion results unobtainable 6 PWME 0 R/W PWM Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5 4 3 -- -- OEB 1 1 0 R R R/W Reserved These bits are always read as 1 and cannot be modified. Output Enable B Enables or disables output on PWM (D/A) channel B. 0: PWM (D/A) channel B output (at the PWX1 pin) is disabled 1: PWM (D/A) channel B output (at the PWX1 pin) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWM (D/A) channel A. 0: PWM (D/A) channel A output (at the PWX0 pin) is disabled 1: PWM (D/A) channel A output (at the PWX0 pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWM (D/A) output. 0: Direct PWM (D/A) output 1: Inverted PWM (D/A) output
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Section 8 14-Bit PWM Timer (PWMX)
Bit 0
Bit Name CKS
Initial Value 0
R/W R/W
Description Clock Select Selects the PWM (D/A) resolution. If the system clock () frequency is 10 MHz, resolutions of 100 ns and 200 ns, can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2
8.4
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. Write: When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. Read: When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lower-byte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT
MOV.W R0, @DACNT ; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0 ; Copy contents of DADRA to R0
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Section 8 14-Bit PWM Timer (PWMX)
Table 8.2
Read and Write Access Methods for 16-Bit Registers
Read Write Word Yes Yes Byte x x
Register Name DADRA and DADRB DACNT
Word Yes Yes
Byte Yes x
[Legend] Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte (first) and lower byte (second). x: This type of access may give incorrect results.
8.5
Operation
A PWM waveform like the one shown in figure 8.2 is output from the PWMX pin. The value in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and the DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 8.3 and 8.4 show the types of waveform output available.
1 conversion cycle (T x 214 (= 16384))
tf
Base cycle (T x 64 or T x 256)
tL
T: Resolution TL = tLn (OS = 0)
n=1 m
(When CFS = 0, m = 256 When CFS = 1, m = 64)
Figure 8.2 PWM D/A Operation
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Section 8 14-Bit PWM Timer (PWMX)
Table 8.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR contains at least a certain minimum value. Table 8.3 Settings and Operation (Examples when = 10 MHz)
Fixed DADR Bits Base Cycle Conversion TL (if OS = 0) ResoluTH (if OS = 1) CKS tion T (s) CFS (s) Cycle (s) 0 0.1 0 6.4 1638.4 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) 3276.8 1. Always low (or high) (DADR = H'0001 to H'03FD) 2. (Data value) x T (DADR = H'0401 to H'FFFD) 1. Always low (or high) (DADR = H'0003 to H'00FF) 2. (Data value) x T (DADR = H'0103 to H'FFFF) PreBit Data cision (Bits) 3 2 1 0 14 12 10 0 0 0 0 0 0 Conversion Cycle* (s) 1638.4 409.6 102.4
1
25.6
14 12 10 14 12 0 0 0 0 0 0 0 0
1638.4 409.6 102.4 3276.8 819.2
1
0.2
0
12.8
10 14 12 10
0
0
0
0
204.8 3276.8
1
51.2
0 0 0 0
0 0
819.2 204.8
Note:
*
This column indicates the conversion cycle when specific DADR bits are fixed.
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Section 8 14-Bit PWM Timer (PWMX)
1 conversion cycle tf1 tf2 tf255 tf256
tL1
tL2
tL3
tL255
tL256
tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) x 64]
1 conversion cycle tf1 tf2 tf63 tf64
tL1
tL2
tL3
tL63
tL64
tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) x 256]
Figure 8.3 Output Waveform (OS = 0, DADR corresponds to TL)
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Section 8 14-Bit PWM Timer (PWMX)
1 conversion cycle
tf1
tf2
tf255
tf256
tH1
tH2
tH3
tH255
tH256
tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH
a. CFS = 0 [base cycle = resolution (T) x 64]
1 conversion cycle
tf1
tf2
tf63
tf64
tH1
tH2
tH3
tH63
tH64
tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) x 256]
Figure 8.4 Output Waveform (OS = 1, DADR corresponds to TH) An example of setting CFS to 1 (basic cycle = resolution (T) x 256) and OS to 1 (PWMX inverted output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional pulse is determined by the following six bits (DA5 to DA0) as shown in figure 8.5. Table 8.4 shows the position of the additional pulse.
DA13 DA12 DA11 DA10 DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CFS 1 1
Basic pulse duty ratio
Additional pulse position
Figure 8.5 D/A Data Register Configuration when CFS = 1 Here, the case of DADR = H'0207 (B'0000 0010 0000 0111) is considered. Figure 8.6 shows an output waveform. Because CFS = 1 and the value of upper eight bits is B'0000 0010, the duty ratio of the basic pulse is 2/256 x (T) of high width.
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Section 8 14-Bit PWM Timer (PWMX)
Since the value of the following six bits is B'0000 01, the additional pulse is output at the position of basic pulse No. 63 as shown in table 8.4. Only 1/256 x (T) of the additional pulse is added to the basic pulse.
One conversion cycle Basic cycle No.0 Basic cycle No.1 Basic cycle No.63
Basic pulse High width: 2/256 x (T)
Additional pulse output position
Basic pulse 2/256 x (T)
Additional pulse 1/256 x (T)
Figure 8.6 Output Waveform when DADR = H'0207 (OS = 1) Note that the case of CFS = 0 (basic cycle = resolution (T) x 64) is similar other than the duty ratio of the basic pulse is determined by the upper six bits, and the position of the additional pulse is determined by the following eight bits.
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Table 8.4
0
1
2
3
4
5
6
7
8
Basic Pulse No. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Position of Pulse to be Added to Basic Pulse (CFS = 1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Lower 6 bits 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Section 8 14-Bit PWM Timer (PWMX)
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REJ09B0241-0100
Section 8 14-Bit PWM Timer (PWMX)
8.6
8.6.1
Usage Note
Module Stop Mode Setting
PWMX operation can be enabled or disabled using the module stop control register. The initial setting is for PWMX operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 18, Power-Down Modes.
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Section 9 16-Bit Free-Running Timer (FRT)
Section 9 16-Bit Free-Running Timer (FRT)
This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods.
9.1
Features
* Selection of four clock sources One of the three internal clocks (/2, /8, or /32), or an external clock input can be selected (enabling use as an external event counter). * Two independent comparators Two independent waveforms can be output. * Four independent input capture channels The rising or falling edge can be selected. Buffer modes can be specified. * Counter clearing The free-running counters can be cleared on compare-match A. * Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM x 2, enabling input capture operations in this interval to be restricted.
TIM8FR1A_010020020700
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Section 9 16-Bit Free-Running Timer (FRT)
Figure 9.1 shows a block diagram of the FRT.
External clock Internal clock
FTCI
/2 /8 /32
OCRAR/F (H/L)
Clock selector
Clock
OCRA (H/L)
Compare-match A
Bus interface
FTOA
Module data bus
Comparator A
FTOB FTIA
FTIB
FTIC
FTID
Control logic
Overflow
Internal data bus
FRC (H/L)
Clear Compare-match B
Comparator B
OCRB (H/L)
Input capture
ICRA (H/L)
ICRB (H/L)
ICRC (H/L)
ICRD (H/L)
Comparator M
Compare-match M
x1 x2
OCRDM L
TCSR
TIER
TCR TOCR
ICIA ICIB ICIC ICID OCIA OCIB FOVI
Interrupt signal
[Legend] OCRA, OCRB: OCRAR, OCRAF: OCRDM: FRC: ICRA to D: TCSR: TIER: TCR: TOCR: Output compare register A, B (16-bit) Output compare register AR, AF (16-bit) Output compare register DM (16-bit) Free-running counter (16-bit) Input capture registers A to D (16-bit) Timer control/status register (8-bit) Timer interrupt enable register (8-bit) Timer control register (8-bit) Timer output compare control register (8-bit)
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer
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Section 9 16-Bit Free-Running Timer (FRT)
9.2
Input/Output Pins
Table 9.1 lists the FRT input and output pins. Table 9.1
Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin
Pin Configuration
Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input
9.3
Register Descriptions
The FRT has the following registers. * * * * * * * * * * * * * * Free-running counter (FRC) Output compare register A (OCRA) Output compare register B (OCRB) Input capture register A (ICRA) Input capture register B (ICRB) Input capture register C (ICRC) Input capture register D (ICRD) Output compare register AR (OCRAR) Output compare register AF (OCRAF) Output compare register DM (OCRDM) Timer interrupt enable register (TIER) Timer control/status register (TCSR) Timer control register (TCR) Timer output compare control register (TOCR)
Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Register selection is controlled by the ICRS bit in TOCR.
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Section 9 16-Bit Free-Running Timer (FRT)
9.3.1
Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 9.3.2 Output Compare Registers A and B (OCRA, OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF. 9.3.3 Input Capture Registers A to D (ICRA to ICRD)
The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is transferred to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then transferred to the buffer register ICRC. To ensure input capture, the input capture pulse width should be at least 1.5 system clocks () for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks (). ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000.
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Section 9 16-Bit Free-Running Timer (FRT)
9.3.4
Output Compare Registers AR and AF (OCRAR, OCRAF)
OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When using the OCRA automatic addition function, do not select internal clock /2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF. 9.3.5 Output Compare Register DM (OCRDM)
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while the ICRDMS bit is set to 1. OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is initialized to H'0000.
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Section 9 16-Bit Free-Running Timer (FRT)
9.3.6
Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit 7 Bit Name ICIAE Initial Value 0 R/W R/W Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled 6 ICIBE 0 R/W Input Capture Interrupt B Enable Selects whether to enable input capture interrupt B request (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. 0: ICIB requested by ICFB is disabled 1: ICIB requested by ICFB is enabled 5 ICICE 0 R/W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. 0: ICIC requested by ICFC is disabled 1: ICIC requested by ICFC is enabled 4 ICIDE 0 R/W Input Capture Interrupt D Enable Selects whether to enable input capture interrupt D request (ICID) when input capture flag D (ICFD) in TCSR is set to 1. 0: ICID requested by ICFD is disabled 1: ICID requested by ICFD is enabled 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled
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Section 9 16-Bit Free-Running Timer (FRT)
Bit 2
Bit Name OCIBE
Initial Value 0
R/W R/W
Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled
1
OVIE
0
R/W
Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled
0
--
0
R
Reserved This bit is always read as 1 and cannot be modified.
9.3.7
Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit 7 Bit Name ICFA Initial Value 0 R/W Description
R/(W)* Input Capture Flag A This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFA when ICFA = 1, then write 0 to ICFA
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Section 9 16-Bit Free-Running Timer (FRT)
Bit 6
Bit Name ICFB
Initial Value 0
R/W
Description
R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] Read ICFB when ICFB = 1, then write 0 to ICFB
5
ICFC
0
R/(W)* Input Capture Flag C This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin, ICFC is set but data is not transferred to ICRC. In buffer operation, ICFC can be used as an external interrupt signal by setting the ICICE bit to 1. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFC when ICFC = 1, then write 0 to ICFC
4
ICFD
0
R/(W)* Input Capture Flag D This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of an input capture signal specified by the IEDGD bit at the FTID input pin, ICFD is set but data is not transferred to ICRD. In buffer operation, ICFD can be used as an external interrupt signal by setting the ICIDE bit to 1. Only 0 can be written to this bit to clear the flag. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFD when ICFD = 1, then write 0 to ICFD
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Section 9 16-Bit Free-Running Timer (FRT)
Bit 3
Bit Name OCFA
Initial Value 0
R/W
Description
R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA
2
OCFB
0
R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB
1
OVF
0
R/(W)* Timer Overflow This status flag indicates that the FRC has overflowed. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF
0
CCLRA
0
R/W
Counter Clear A This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared at compare-match A
Note *
Only 0 can be written to clear the flag.
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Section 9 16-Bit Free-Running Timer (FRT)
9.3.8
Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source.
Bit 7 Bit Name IEDGA Initial Value 0 R/W R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA). 0: Capture on the falling edge of FTIA 1: Capture on the rising edge of FTIA 6 IEDGB 0 R/W Input Edge Select B Selects the rising or falling edge of the input capture B signal (FTIB). 0: Capture on the falling edge of FTIB 1: Capture on the rising edge of FTIB 5 IEDGC 0 R/W Input Edge Select C Selects the rising or falling edge of the input capture C signal (FTIC). 0: Capture on the falling edge of FTIC 1: Capture on the rising edge of FTIC 4 IEDGD 0 R/W Input Edge Select D Selects the rising or falling edge of the input capture D signal (FTID). 0: Capture on the falling edge of FTID 1: Capture on the rising edge of FTID 3 BUFEA 0 R/W Buffer Enable A Selects whether ICRC is to be used as a buffer register for ICRA. 0: ICRC is not used as a buffer register for ICRA 1: ICRC is used as a buffer register for ICRA 2 BUFEB 0 R/W Buffer Enable B Selects whether ICRD is to be used as a buffer register for ICRB. 0: ICRD is not used as a buffer register for ICRB 1: ICRD is used as a buffer register for ICRB
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Section 9 16-Bit Free-Running Timer (FRT)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W
Description Clock Select 1, 0 Select clock source for FRC. 00: /2 internal clock source 01: /8 internal clock source 10: /32 internal clock source 11: External clock source (counting at FTCI rising edge)
9.3.9
Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C.
Bit 7 Bit Name ICRDMS Initial Value 0 R/W R/W Description Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0: The normal operating mode is specified for ICRD 1: The operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R/W Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read from or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0: ICRA, ICRB, and ICRC are selected 1: OCRAR, OCRAF, and OCRDM are selected
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Section 9 16-Bit Free-Running Timer (FRT)
Bit 4
Bit Name OCRS
Initial Value 0
R/W R/W
Description Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected
3
OEA
0
R/W
Output Enable A Enables or disables output of the output compare A output pin (FTOA). 0: Output compare A output is disabled 1: Output compare A output is enabled
2
OEB
0
R/W
Output Enable B Enables or disables output of the output compare B output pin (FTOB). 0: Output compare B output is disabled 1: Output compare B output is enabled
1
OLVLA
0
R/W
Output Level A Selects the level to be output at the output compare A output pin (FTOA) in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. 0: 0 is output at compare-match A 1: 1 is output at compare-match A
0
OLVLB
0
R/W
Output Level B Selects the level to be output at the output compare B output pin (FTOB) in response to compare-match B (signal indicating a match between the FRC and OCRB values). 0: 0 is output at compare-match B 1: 1 is output at compare-match B
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Section 9 16-Bit Free-Running Timer (FRT)
9.4
9.4.1
Operation
Pulse Output
Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software.
FRC
H'FFFF
Counter clear
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 9.2 Example of Pulse Output
9.5
9.5.1
Operation Timing
FRC Increment Timing
Figure 9.3 shows the FRC increment timing with an internal clock source. Figure 9.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks ().
Internal clock
FRC input clock
FRC
N-1
N
N+1
Figure 9.3 Increment Timing with Internal Clock Source
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Section 9 16-Bit Free-Running Timer (FRT)
External clock input pin
FRC input clock
FRC
N
N+1
Figure 9.4 Increment Timing with External Clock Source 9.5.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 9.5 shows the timing of this operation for compare-match A.
FRC
N
N+1
N
N+1
OCRA
N
N
Compare-match A signal
Clear*
OLVLA
Output compare A output pin FTOA
Note : * Indicates instruction execution by software.
Figure 9.5 Timing of Output Compare A Output
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Section 9 16-Bit Free-Running Timer (FRT)
9.5.3
FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 9.6 shows the timing of this operation.
Compare-match A signal
FRC
N
H'0000
Figure 9.6 Clearing of FRC by Compare-Match A Signal 9.5.4 Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is selected.
Input capture input pin Input capture signal
Figure 9.7 Input Capture Input Signal Timing (Usual Case)
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Section 9 16-Bit Free-Running Timer (FRT)
If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (). Figure 9.8 shows the timing for this case.
Read cycle of ICRA to ICRD T1 T2
Input capture input pin
Input capture signal
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) 9.5.5 Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 9.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
FTIA
Input capture signal
FRC
n
n+1
N
N+1
ICRA
M
n
n
N
ICRC
m
M
M
n
Figure 9.9 Buffered Input Capture Timing
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Section 9 16-Bit Free-Running Timer (FRT)
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (). Figure 9.10 shows the timing when BUFEA = 1.
CPU read cycle of ICRA or ICRC T1 T2
FTIA
Input capture signal
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1)
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Section 9 16-Bit Free-Running Timer (FRT)
9.5.6
Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 9.11 shows the timing of setting the ICFA to ICFD flag.
Input capture signal
ICFA to ICFD
FRC
N
ICRA to ICRD
N
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
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Section 9 16-Bit Free-Running Timer (FRT)
9.5.7
Timing of Output Compare Flag (OCF) setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 9.12 shows the timing of setting the OCFA or OCFB flag.
FRC
N
N+1
OCRA, OCRB
N
Compare-match signal
OCFA, OCFB
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
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Section 9 16-Bit Free-Running Timer (FRT)
9.5.8
Timing of FRC Overflow Flag Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 9.13 shows the timing of setting the OVF flag.
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 9.13 Timing of Overflow Flag (OVF) Setting
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Section 9 16-Bit Free-Running Timer (FRT)
9.5.9
Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 9.14 shows the OCRA write timing.
FRC
N
N +1
OCRA
N
N+A
OCRAR, OCRAF
A
Compare-match signal
Figure 9.14 OCRA Automatic Addition Timing
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Section 9 16-Bit Free-Running Timer (FRT)
9.5.10
Mask Signal Generation Timing
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 9.15 shows the timing of setting the mask signal. Figure 9.16 shows the timing of clearing the mask signal.
Input capture signal
Input capture mask signal
Figure 9.15 Timing of Input Capture Mask Signal Setting
FRC
N
N+1
ICRD + OCRDM x 2
N
Compare-match signal
Input capture mask signal
Figure 9.16 Timing of Input Capture Mask Signal Clearing
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Section 9 16-Bit Free-Running Timer (FRT)
9.6
Interrupt Sources
The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts. Table 9.2
Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI
FRT Interrupt Sources
Interrupt Source Input capture of ICRA Input capture of ICRB Input capture of ICRC Input capture of ICRD Interrupt Flag ICFA ICFB ICFC ICFD Priority High
Compare match of OCRA OCFA Compare match of OCRB OCFB Overflow of FRC OVF Low
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Section 9 16-Bit Free-Running Timer (FRT)
9.7
9.7.1
Usage Notes
Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 9.17 shows the timing for this type of conflict.
Write cycle of FRC T1 T2
Address
FRC address
Internal write signal
Counter clear signal
FRC
N
H'0000
Figure 9.17 FRC Write-Clear Conflict
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Section 9 16-Bit Free-Running Timer (FRT)
9.7.2
Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 9.18 shows the timing for this type of conflict.
Write cycle of FRC
T1
T2
Address
FRC address
Internal write signal
FRC input clock
FRC
N
M
Write data
Figure 9.18 FRC Write-Increment Conflict 9.7.3 Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 9.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 9.20 shows the timing for this type of conflict.
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Section 9 16-Bit Free-Running Timer (FRT)
Write cycle of OCR
T1
T2
Address
OCR address
Internal write signal
FRC
N
N+1
OCR
N
M
Write data Compare-match signal Disabled
Figure 9.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used)
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Section 9 16-Bit Free-Running Timer (FRT)
Write cycle of OCRAR/OCRAF T1 T2
Address
OCRAR (OCRAF) address
Internal write signal
OCRAR (OCRAF)
Old data
New data
Compare-match signal
Disabled
FRC
N
N+1
OCRA
N Automatic addition is not performed because compare-match signals are disabled.
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function is Used)
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Section 9 16-Bit Free-Running Timer (FRT)
9.7.4
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 9.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 9.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also cause FRC to increment. Table 9.3 Switching of Internal Clock and FRC Operation
No. 1
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low
FRC Operation
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
CKS bit rewrite
2
Switching from low to high
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
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Section 9 16-Bit Free-Running Timer (FRT)
No. 3
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low
FRC Operation
Clock before switchover
Clock after switchover
*
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
4
Switching from high to high
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note: *
Generated on the assumption that the switchover is a falling edge; FRC is incremented.
9.7.5
Module Stop Mode Setting
FRT operation can be enabled or disabled using the module stop control register. The initial setting is for FRT operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 18, Power-Down Modes.
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Section 9 16-Bit Free-Running Timer (FRT)
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Section 10 8-Bit Timer (TMR)
Section 10 8-Bit Timer (TMR)
This LSI has three channels of on-chip 8-bit timer modules (TMR_0, TMR_1, and TMR_Y) made up of 8-bit counters. The 8-bit timer module can count external events, and can also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
10.1
Features
* Selection of clock sources TMR_0, TMR_1: The counter input clock can be selected from six internal clocks and an external clock TMR_Y: The counter input clock can be selected from three internal clocks and an external clock * Selection of three ways to clear the counters The counters can be cleared on compare-match A or compare-match B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. (The TMR_Y does not have a timer output pin.) * Cascading of TMR_0 and TMR_1 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, compare-match B, and overflow
TIMH261A_010020020700
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Section 10 8-Bit Timer (TMR)
Figures 10.1 and 10.2 show block diagrams of the 8-bit timer module.
External clock sources TMCI0 TMCI1 Internal clock sources
TMR_0 /2, /8 /32, /64 /256, /1024
TMR_1 /2, /8 /64, /128 /1024, /2048
Clock 1 Clock 0 Clock selecter TCORA_0 Compare-match A1 Compare-match A0 Comparator A_0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B_0 TMO1 TMRI1 Control logic TCORB_0 TCORB_1 Comparator B_1 TCORA_1
Comparator A_1
TMO0 TMRI0
TCNT_0
TCNT_1
TCSR_0
TCSR_1
TCR_0 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 [Legend] TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0:
TCR_1
Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0
TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1:
Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1
Figure 10.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)
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Internal bus
Section 10 8-Bit Timer (TMR)
External clock source TMCIY
Internal clock sources /4 /256 /2048
Clock selecter
Clock Y
TCORA_Y
Compare-match AY
Comparator A_Y
Overflow Y
TCNT_Y
Clear Y
Internal bus
TMRIY
Control logic
Compare-match BY
Comparator B_Y
TCORB_Y
TCSR_Y
TCR_Y
TISR
Interrupt signals CMIAY CMIBY OVIY [Legend] TCORA_Y: TCORB_Y: TCNT_Y: TCSR_Y: TCR_Y: TISR: Time constant register A_Y Time constant register B_Y Timer counter_Y Timer control/status register_Y Timer control register_Y Timer input select register
Figure 10.2 Block Diagram of 8-Bit Timers (TMR_Y)
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Section 10 8-Bit Timer (TMR)
10.2
Input/Output Pins
Table 10.1 summarizes the input and output pins of the TMR. Table 10.1 Pin Configuration
Channel Name TMR_0 Timer output Timer clock input Timer reset input TMR_1 Timer output Timer clock input Timer reset input TMR_Y Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Function
Output Output controlled by compare-match Input Input External clock input for the counter External reset input for the counter
Output Output controlled by compare-match Input Input External clock input for the counter External reset input for the counter External clock input for the counter/ external reset input for the counter
Timer clock/reset input TMIY Input (TMCIY/TMRIY)
10.3
Register Descriptions
The TMR has the following registers. For details on the serial timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR). * * * * * * Timer counter (TCNT) Time constant register A (TCORA) Time constant register B (TCORB) Timer control register (TCR) Timer control/status register (TCSR) Timer input select register (TISR)*
Note: * TISR is only for the TMR_Y. 10.3.1 Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, comparematch A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00.
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Section 10 8-Bit Timer (TMR)
10.3.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 10.3.3 Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.
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Section 10 8-Bit Timer (TMR)
10.3.4
Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests.
Bit 7 Bit Name Initial Value R/W Description CMIEB 0 R/W Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W Counter Clear 1, 0 R/W These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W Clock Select 2 to 0 R/W These bits select the clock input to TCNT and count R/W condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 10.2.
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Section 10 8-Bit Timer (TMR)
Table 10.2 Clock Input to TCNT and Count Condition
TCR Channel CKS2 TMR_0 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 STCR ICKS1 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- ICKS0 -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0*
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Section 10 8-Bit Timer (TMR)
TCR Channel CKS2 TMR_Y 0 0 0 0 1 Common 1 1 1 Note: * CKS1 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 1 0 1
STCR ICKS1 -- -- -- -- -- -- -- -- ICKS0 -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /4 Increments at falling edge of internal clock /256 Increments at falling edge of internal clock /2048 Disables clock input Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock.
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated.
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Section 10 8-Bit Timer (TMR)
10.3.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. * TCSR_0
Bit 7 Bit Name Initial Value R/W CMFB 0 Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing conditions] * Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_0 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4
ADTE
0
R/W
A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled
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Section 10 8-Bit Timer (TMR)
Bit 3 2
Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W
Description Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
1 0
OS1 OS0
0 0
R/W R/W
Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
Note:
*
Only 0 can be written for clearing the flag.
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Section 10 8-Bit Timer (TMR)
* TCSR_1
Bit 7 Bit Name Initial Value R/W CMFB 0 Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing conditions * Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4 3 2
-- OS3 OS2
1 0 0
R R/W R/W
Reserved This bit is always read as 1 and cannot be modified. Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
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Section 10 8-Bit Timer (TMR)
Bit 1 0
Bit Name Initial Value R/W OS1 OS0 0 0 R/W R/W
Description Output Select 1, 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
Note:
*
Only 0 can be written for clearing the flag.
* TCSR_Y
Bit 7 Bit Name Initial Value R/W CMFB 0
1
Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing conditions] * Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing conditions] * Read CMFA when CMFA = 1, then write 0 in CMFA
1
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
1
4
0
R
Reserved This bit is always read as 0 and cannot be modified.
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Section 10 8-Bit Timer (TMR)
Bit 3 2
Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W
Description Output Select 3, 2
2 These bits specify how the TMOY pin* output level is to be changed by compare-match B of TCORB_Y and TCNT_Y.
00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1, 0
2 These bits specify how the TMOY pin* output level is to be changed by compare-match A of TCORA_Y and TCNT_Y.
00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Notes: 1. Only 0 can be written for clearing the flag. 2. This product does not have a TMOY external output pin.
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Section 10 8-Bit Timer (TMR)
10.3.6
Timer Input Select Register (TISR)
TISR enables or disables to input a signal on the external counter clock/external counter reset input pin.
Bit 7 to 1 0 Bit Name Initial Value R/W -- All 1 Description
R/(W) Reserved The initial value should not be modified.
IS
0
R/W
Input Select Enables or disables to input a signal to be used as an external clock or an external reset for the TMR_Y counter on the TMIY (TMCIY/TMRIY) pin. 0: Disables a signal input on the TMIY (TMCIY/TMRIY) pin 1: Enables a signal input on the TMIY (TMCIY/TMRIY) pin
10.4
10.4.1
Operation
Pulse Output
Figure 10.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software.
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Section 10 8-Bit Timer (TMR)
TCNT H'FF TCORA TCORB H'00 Counter clear
TMO
Figure 10.3 Pulse Output Example
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Section 10 8-Bit Timer (TMR)
10.5
10.5.1
Operation Timing
TCNT Count Timing
Figure 10.4 shows the TCNT count timing with an internal clock source. Figure 10.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks () for a single edge and at least 2.5 system clocks () for both edges. The counter will not increment correctly if the pulse width is less than these values.
Internal clock
TCNT input clock
TCNT
N-1
N
N+1
Figure 10.4 Count Timing for Internal Clock Input
External clock input pin
TCNT input clock
TCNT
N-1
N
N+1
Figure 10.5 Count Timing for External Clock Input (Both Edges)
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Section 10 8-Bit Timer (TMR)
10.5.2
Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 10.6 shows the timing of CMF flag setting.
TCNT
N
N+1
TCOR Compare-match signal
N
CMF
Figure 10.6 Timing of CMF Setting at Compare-Match 10.5.3 Timing of Timer Output at Compare-Match
When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 10.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal.
Compare-match A signal
Timer output pin
Figure 10.7 Timing of Toggled Timer Output by Compare-Match A Signal
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Section 10 8-Bit Timer (TMR)
10.5.4
Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.8 shows the timing of clearing the counter by a compare-match.
Compare-match signal
TCNT
N
H'00
Figure 10.8 Timing of Counter Clear by Compare-Match 10.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 10.9 shows the timing of clearing the counter by an external reset input.
External reset input pin
Clear signal
TCNT
N-1
N
H'00
Figure 10.9 Timing of Counter Clear by External Reset Input
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Section 10 8-Bit Timer (TMR)
10.5.6
Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 10.10 shows the timing of OVF flag setting.
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 10.10 Timing of OVF Flag Setting
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Section 10 8-Bit Timer (TMR)
10.6
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit count mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of channel 1 (compare-match count mode). 10.6.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. Setting of Compare-Match Flags: * The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. Counter Clear Specification: * If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently.
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Section 10 8-Bit Timer (TMR)
Pin Output: * Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. * Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 10.6.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel.
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Section 10 8-Bit Timer (TMR)
10.7
Interrupt Sources
TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. Table 10.3 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 10.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X
Channel Name TMR_0 CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY Interrupt Source TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF Low Interrupt Priority High
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Section 10 8-Bit Timer (TMR)
10.8
10.8.1
Usage Notes
Conflict between TCNT Write and Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 10.11, clearing takes priority, so that the counter is cleared and the write is not performed.
TCNT write cycle by CPU T1 T2
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
H'00
Figure 10.11 Conflict between TCNT Write and Clear
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Section 10 8-Bit Timer (TMR)
10.8.2
Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 10.12, the write takes priority and the counter is not incremented.
TCNT write cycle by CPU
T1
T2
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 10.12 Conflict between TCNT Write and Increment
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Section 10 8-Bit Timer (TMR)
10.8.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 10.13, the TCOR write takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data Compare-match signal
Disabled
Figure 10.13 Conflict between TCOR Write and Compare-Match
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Section 10 8-Bit Timer (TMR)
10.8.4
Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 10.4. Table 10.4 Timer Output Priorities
Output Setting Toggle output 1 output 0 output No change Low Priority High
10.8.5
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when internal clocks are switched. Table 10.5 shows the relationship between the timing at which internal clocks are switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is always monitored. If the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and TCNT is incremented. The erroneous incrementation of TCNT can also happen when switching between internal and external clocks.
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Section 10 8-Bit Timer (TMR)
Table 10.5 Switching of Internal Clocks and TCNT Operation
Timing of Changing Signal Levels by CKS1 and CKS0 Signal level switching from low to low level*1
No. 1
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock
TCNT
N CKS bit rewrite
N+1
2
Signal level switching from low to high level2
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
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Section 10 8-Bit Timer (TMR)
No. 3
Timing of Switchover by Means of CKS1 and CKS0 Bits Signal level switching from high to low level3
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock *4
TCNT
N
N+1 CKS bit rewrite
N+2
4
Signal level switching from high to high level
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2 CKS bit rewrite
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
10.8.6
Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided.
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Section 10 8-Bit Timer (TMR)
10.8.7
Module Stop Mode Setting
TMR operation can be enabled or disabled using the module stop control register. The initial setting is for TMR operation to be halted. Register access is enabled by canceling the module stop mode. For details, refer to section 18, Power-Down Modes.
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Section 10 8-Bit Timer (TMR)
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Section 11 Watchdog Timer (WDT)
Section 11 Watchdog Timer (WDT)
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can output an overflow signal (RESO) externally. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 is shown in figure 11.1.
11.1
Features
* Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, an internal reset or an internal NMI interrupt is generated. * When the LSI is selected to be internally reset at counter overflow, a low level signal is output from the RESO pin if the counter overflows. (Available only for the H8S/2144B.) Internal Timer Mode: * If the counter overflows, an internal timer interrupt (WOVI) is generated.
WDT0102A_010020020700
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Section 11 Watchdog Timer (WDT)
WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1
Interrupt control Reset control
Overflow
Clock
Clock selection
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
TCNT_0
TCSR_0
Module bus
Bus interface
WDT_0
WOVI1 (Interrupt request signal)
Internal NMI (Interrupt request signal*2)
Interrupt control Reset control
Overflow
Clock
Clock selection
RESO signal*1 Internal reset signal*1
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256
TCNT_1
TCSR_1
Module bus
Bus interface
WDT_1
[Legend]
TCSR_0: TCNT_0: TCSR_1: TCNT_1:
Timer control/status register_0 Timer counter_0 Timer control/status register_1 Timer counter_1
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal first resets the WDT in which the overflow has occurred first. [H8S/2144B] 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1.
Figure 11.1 Block Diagram of WDT
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Internal bus
Internal bus
Section 11 Watchdog Timer (WDT)
11.2
Input/Output Pins
The WDT has the pins listed in table 11.1. Table 11.1 Pin Configuration
Name Reset output pin Symbol RESO I/O Output Input Function Outputs the counter overflow signal in watchdog timer mode (Available only for the H8S/2144B) Inputs the clock pulses to the WDT_1 prescaler counter
External sub-clock EXCL input pin
11.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, refer to section 11.6.1, Notes on Register Access. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR). * Timer counter (TCNT) * Timer control/status register (TCSR) 11.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is cleared to 0.
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Section 11 Watchdog Timer (WDT)
11.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0
Bit 7 Initial Bit Name Value OVF 0 R/W R/(W)*
1
Description Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * When TCSR is read when OVF = 1* , then 0 is written to OVF When 0 is written to TME
2
6
WT/IT
0
R/W
Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode
5
TME
0
R/W
Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
4 3
--
0
R/(W) R/W
Reserved The initial value should not be modified. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested
RST/NMI 0
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Section 11 Watchdog Timer (WDT)
Bit 2 1 0
Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W
Description Clock Select 2 to 0 Selects the clock source to be input to. The overflow frequency for = 10 MHz is enclosed in parentheses. 000: /2 (frequency: 51.2 s) 001: /64 (frequency: 1.64 ms) 010: /128 (frequency: 3.28 ms) 011: /512 (frequency: 13.1 ms) 100: /2048 (frequency: 52.4 ms) 101: /8192 (frequency: 209.7 ms) 110: /32768 (frequency: 0.84 s) 111: /131072 (frequency: 3.36 s)
Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice.
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Section 11 Watchdog Timer (WDT)
* TCSR_1
Bit 7 Bit Name Initial Value R/W OVF 0
1
Description
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] When TCSR is read when OVF = 1* , then 0 is written to OVF When 0 is written to TME 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested
2
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Section 11 Watchdog Timer (WDT)
Bit 2 1 0
Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W
Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for = 10 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (frequency: 51.2 s) 001: /64 (frequency: 1.64 ms) 010: /128 (frequency: 3.28 ms) 011: /512 (frequency: 13.1 ms) 100: /2048 (frequency: 52.4 ms) 101: /8192 (frequency: 209.7 ms) 110: /32768 (frequency: 0.84 s) 111: /131072 (frequency: 3.36 s) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: /256 (cycle: 2 s)
Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice.
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Section 11 Watchdog Timer (WDT)
11.4
11.4.1
Operation
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 11.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin remains high. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. Note: * The RESO pin is available only for the H8S/2144B.
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Section 11 Watchdog Timer (WDT)
TCNT value
Overflow
H'FF
H'00
WT/IT = 1 TME = 1 Write H'00 to TCNT
OVF = 1*
RESO and internal reset signals generated
Time
WT/IT = 1 Write H'00 to TME = 1 TCNT
RESO*2 signal 132 system clocks
Internal reset signal 518 system clocks [Legend] WT/IT: Timer mode select bit TME: Timer enable bit OVF: Overflow flag
Notes: 1. 2. After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Available only for the H8S/2144B.
Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation
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Section 11 Watchdog Timer (WDT)
11.4.2
Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 11.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 11.4.
TCNT value
H'FF
Overflow Overflow Overflow Overflow
H'00
WT/IT = 0 TME = 1 WOVI WOVI WOVI
WOVI
Time
WOVI : Internal timer interrupt request occurrence
Figure 11.3 Interval Timer Mode Operation
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 11.4 OVF Flag Set Timing
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Section 11 Watchdog Timer (WDT)
11.4.3
RESO Signal Output Timing (Available for H8S/2144B)
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 11.5.
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
RESO signal*
132 states
Internal reset signal
518 states
Note: * Available only for the H8S/2144B.
Figure 11.5 Output Timing of RESO signal
11.5
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow. Table 11.2 WDT Interrupt Source
Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF
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Section 11 Watchdog Timer (WDT)
11.6
11.6.1
Usage Notes
Notes on Register Access
The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 11.6 to write to TCNT or TCSR. To write to TCNT, the upper bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the upper bytes must contain the value H'A5 and the lower bytes must contain the write data.
15 Address : H'FFA8 0 H'5A 87 Write data 0
15 Address : H'FFA8 0 H'A5 87 Write data 0
Figure 11.6 Writing to TCNT and TCSR (WDT_0) Reading from TCNT and TCSR (Example of WDT_0): These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT.
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Section 11 Watchdog Timer (WDT)
11.6.2
Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.7 shows this operation.
TCNT write cycle T1 T2
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.7 Conflict between TCNT Write and Increment 11.6.3 Changing Values of CKS2 to CKS0 Bits
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode.
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Section 11 Watchdog Timer (WDT)
11.6.5
System Reset by RESO Signal (Available for H8S/2144B)
Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 11.8.
This LSI Reset input RES
Reset signal for entire system
RESO
Figure 11.8 Sample Circuit for Resetting System by RESO Signal 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes
When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and sub-active or watch mode, the counter does not display the correct value due to internal clock switching. Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing timing is delayed for approximately two to three clock cycles. Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not supplied until stabilized internal oscillation is available because the main clock oscillator is halted in sub-clock mode. The counter is therefore prevented from incrementing for the time specified by the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing counter value differences for this time. Special care must be taken when using WDT_1 as a clock counter. Note that no counter value difference is produced while operated in the same mode.
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Section 12 Serial Communication Interface (SCI and IrDA)
Section 12 Serial Communication Interface (SCI and IrDA)
This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function) in asynchronous mode. SCI_2 can handle communication using the waveform based on the Infrared Data Association (IrDA) standard version 1.0.
12.1
Features
* Choice of asynchronous or clock synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * The on-chip baud rate generator allows any bit rate to be selected An external clock can be selected as a transfer clock source. * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources -- transmit-end, transmit-data-empty, receive-data-full, and receive error Asynchronous Mode: * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error
SCI0022B_000020020700
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Section 12 Serial Communication Interface (SCI and IrDA)
Clock Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors * Serial data communication with other LSIs that have the clock synchronized communication function A block diagram of the SCI is shown in figure 12.1.
Internal data bus
Bus interface
Module data bus
RDR
TDR
SCMR SSR SCR
BRR
Baud rate generator
RxD
RSR
TSR
SMR Transmission/ reception control
/4 /16 /64
TxD
Parity check
Parity generation
Clock
External clock
SCK
[Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register
TEI TXI RXI ERI
SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register
Figure 12.1 Block Diagram of SCI
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Section 12 Serial Communication Interface (SCI and IrDA)
12.2
Input/Output Pins
Table 12.1 shows the input/output pins for each SCI channel. Table 12.1 Pin Configuration
Channel 0 Symbol* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 2 SCK2 RxD2/IrRxD TxD2/IrTxD Note * Input/Output Input/Output Input Output Input/Output Input Output Input/Output Input Output Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input (normal/IrDA) Channel 2 transmit data output (normal/IrDA)
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.
12.3
Register Descriptions
The SCI has the following registers for each channel. * * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit data register (TDR) Transmit shift register (TSR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Serial interface mode register (SCMR) Bit rate register (BRR) Keyboard comparator control register (KBCOMP)
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 12.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 12.3.3 Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. 12.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock source.
Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clock synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
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Section 12 Serial Communication Interface (SCI and IrDA)
Bit 2
Bit Name MP
Initial Value 0
R/W R/W
Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode.
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 1,0 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR.
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 12.8, Interrupt Sources.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 12.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled.
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Section 12 Serial Communication Interface (SCI and IrDA)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0 These bits select the clock source and SCK pin function. Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clock synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.)
[Legend] X: Don't care
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared.
Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write When 0 is written to TDRE after reading TDRE = 1
[Clearing conditions] * 6 RDRF 0 R/(W)*
Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1
[Clearing conditions] *
The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] * When the next data is received while RDRF = 1 When 0 is written to ORER after reading ORER = 1
[Clearing condition] *
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Section 12 Serial Communication Interface (SCI and IrDA)
Bit 4
Bit Name FER
Initial Value 0
R/W R/(W)*
Description Framing Error [Setting condition] * * When the stop bit is 0 When 0 is written to FER after reading FER = 1 [Clearing condition]
In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] * When a parity error is detected during reception When 0 is written to PER after reading PER = 1
[Clearing condition] * 2 TEND 1 R
Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE =1
[Clearing conditions] * 1 MPB 0 R
Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame.
Note: *
Only 0 can be written, to clear the flag.
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.8
Serial Interface Mode Register (SCMR)
SCMR selects SCI functions and its format.
Bit 7 to 4 3 SDIR 0 R/W Bit Name -- Initial Value All 1 R/W R Description Reserved These bits are always read as 1 and cannot be modified. Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 -- 1 R Reserved This bit is always read as 1 and cannot be modified. 0 SMIF 0 R/W Serial Communication Interface Mode Select: 0: Normal asynchronous or clock synchronous mode 1: Reserved mode
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clock synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 12.2 Relationships between N Setting in BRR and Bit Rate B
Mode Asynchronous mode
B= 64 x 2
Bit Rate
x 10
2n-1 6
Error
x (N+1)
Error (%) = {
x 106 - 1 } x 100
B x 64 x 2
2n-1
x (N+1)
Clock synchronous mode
B= 64 x 2
x 106
2n-1
--
x (N+1)
[Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: Determined by the SMR settings shown in the following table. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the maximum bit rate settable for each frequency. Table 12.6 shows sample N settings in BRR in clock synchronous mode. Tables 12.5 and 12.7 show the maximum bit rates with external clock input.
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Section 12 Serial Communication Interface (SCI and IrDA)
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency (MHz) 2 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 1 1 0 0 0 0 0 0 -- -- -- 2.097152 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 --
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Section 12 Serial Communication Interface (SCI and IrDA)
Operating Frequency (MHz) 3.6864 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
[Legend] --: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 --
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Section 12 Serial Communication Interface (SCI and IrDA)
Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
[Legend] --: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 -- N 248 181 90 181 90 181 90 45 22 13 -- Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 -- n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 16 16 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00
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Section 12 Serial Communication Interface (SCI and IrDA)
Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 166 233 166 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
[Legend] --: Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%.
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Section 12 Serial Communication Interface (SCI and IrDA)
Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 Maximum Bit Rate (bit/s) 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000
(MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8
n 0 0 0 0 0 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0 0 0 0 0 0
(MHz) 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20
n 0 0 0 0 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0 0 0 0 0
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
(MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 External Input Maximum Bit Clock (MHz) Rate (bit/s) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 15.000 1.5360 1.8432 2.0000 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 (MHz) 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Maximum Bit Clock (MHz) Rate (bit/s) 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500
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Section 12 Serial Communication Interface (SCI and IrDA)
Table 12.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M [Legend] Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1* 0 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* -- -- -- 1 1 0 0 0 0 0 0 -- -- -- 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n 8 N n 10 N n 16 N n 20 N
Table 12.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode)
(MHz) 2 4 6 8 10 External Input Maximum Bit Clock (MHz) Rate (bit/s) 0.3333 0.6667 1.0000 1.3333 1.6667 333333.3 666666.7 1000000.0 1333333.3 1666666.7 (MHz) 12 14 16 18 20 External Input Maximum Bit Clock (MHz) Rate (bit/s) 2.0000 2.3333 2.6667 3.0000 3.3333 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3
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Section 12 Serial Communication Interface (SCI and IrDA)
12.3.10 Keyboard Comparator Control Register (KBCOMP) KBCOMP selects the functions of the SCI and A/D converter.
Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Specifies SCI_2 I/O pins for either normal SCI or IrDA. 0: TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2 pins, respectively 1: TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD pins, respectively 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 These bits specify the high-level width of the clock pulse during IrTxD output pulse encoding when the IrDA function is enabled. 000: B x 3/16 (B: Bit rate) 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 3 2 1 0 KBADE KBCH2 KBCH1 KBCH0 0 0 0 0 R/W R/W R/W R/W Bits related to the A/D converter For details, refer to section 14.3.4, Keyboard Comparator Control Register (KBCOMP).
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Section 12 Serial Communication Interface (SCI and IrDA)
12.4
Operation in Asynchronous Mode
Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception.
Idle state (mark state)
1
Serial data
LSB 0 Start bit
1 bit
MSB
D1 D2 D3 D4 D5 D6 D7 0/1
Parity bit 1 bit or none
1
D0
1
1
Stop bit
Transmit/receive data
7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 12.4.1 Data Transfer Format
Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 12.5, Multiprocessor Communication Function.
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Section 12 Serial Communication Interface (SCI and IrDA)
Table 12.8 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 Serial Transmit/Receive Format and Frame Length STOP 0 1 2 3 4 5 6 7 8 9 10 11 12
PE 0
MP 0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
--
1
0
S
8-bit data
MPB STOP
0
--
1
1
S
8-bit data
MPB STOP STOP
1
--
1
0
S
7-bit data
MPB STOP
1
--
1
1
S
7-bit data
MPB STOP STOP
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Section 12 Serial Communication Interface (SCI and IrDA)
12.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the reception margin in asynchronous mode is determined by formula (1) below.
M = } (0.5 -
1 2N
)-
D - 0.5 (1 + F) - (L - 0.5) F } x 100 N
[%]
... Formula (1)
M: Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0.5 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875 %
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0
Receive data (RxD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
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Section 12 Serial Communication Interface (SCI and IrDA)
12.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4.
SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)
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Section 12 Serial Communication Interface (SCI and IrDA)
12.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When an external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer/receive format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[4]
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[1]
Set data transfer/receive format in SMR and SCMR Set value in BRR
[2]
[3]
Wait
No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits

Figure 12.5 Sample SCI Initialization Flowchart
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Section 12 Serial Communication Interface (SCI and IrDA)
12.4.5
Data Transmission (Asynchronous Mode)
Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 12.7 shows a sample flowchart for transmission in asynchronous mode.
Start bit Data Parity Stop Start bit bit bit Data Parity Stop bit bit
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
1 Idle state (mark state)
TDRE TEND
TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine
TEI interrupt request generated
1 frame
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8Bit Data, Parity, One Stop Bit)
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure:
No
TDRE = 1
Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
Read TEND flag in SSR
No
TEND = 1
Yes
No Break output? Yes Clear DR to 0 and set DDR to 1
[4]
Clear TE bit in SCR to 0

Figure 12.7 Sample Serial Transmission Flowchart
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Section 12 Serial Communication Interface (SCI and IrDA)
12.4.6
Serial Data Reception (Asynchronous Mode)
Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1 Idle state (mark state)
RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine
ERI interrupt request generated by framing error
1 frame
Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 12 Serial Communication Interface (SCI and IrDA)
Table 12.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flow chart for serial data reception. Table 12.9 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin.
Read ORER, PER, and FER flags in SSR
No
RDRF = 1
Yes
Read receive data in RDR, and clear RDRF flag in SSR to 0
[4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. [Legend] : Logical OR
No
All data received?
[5]
Yes
Clear RE bit in SCR to 0

Figure 12.9 Sample Serial Reception Flowchart (1)
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Section 12 Serial Communication Interface (SCI and IrDA)
[3] Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
No PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 12.9 Sample Serial Reception Flowchart (2)
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Section 12 Serial Communication Interface (SCI and IrDA)
12.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 12 Serial Communication Interface (SCI and IrDA)
Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) ID transmission cycle = receiving station specification [Legend] MPB: Multiprocessor bit Receiving station C (ID = 03) H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Receiving station D (ID = 04)
Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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Section 12 Serial Communication Interface (SCI and IrDA)
12.5.1
Multiprocessor Serial Data Transmission
Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0.
No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR
Clear TDRE flag to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes [4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0

Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart
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Section 12 Serial Communication Interface (SCI and IrDA)
12.5.2
Multiprocessor Serial Data Reception
Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception.
Start bit Data (ID1) MPB Stop bit Start bit Data (Data 1) Stop MPB bit
1
1
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1 Idle state (mark state)
MPIE
RDRF
RDR value
MPIE = 0
ID1
RXI interrupt request (multiprocessor interrupt) generated
RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine
If not this station's ID, MPIE bit is set to 1 again
RXI interrupt request is not generated, and RDR retains its state
(a) Data does not match station's ID
1
Start bit
0 D0 D1
Data (ID2)
D7
Stop MPB bit
1 1
Start bit
0 D0
Data (Data 2)
D1
D7
Stop MPB bit
0
1
1 Idle state (mark state)
MPIE
RDRF
RDR value
ID1
MPIE = 0
ID2
Data 2 MPIE bit set to 1 again
RXI interrupt request (multiprocessor interrupt) generated
RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine
Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine
(b) Data matches station's ID
Figure 12.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value.
Set MPIE bit in SCR to 1
Read ORER and FER flags in SSR
[2]
FER ORER = 1
Yes
No
Read RDRF flag in SSR [3]
No
RDRF = 1
Yes
Read receive data in RDR No
This station's ID?
Yes
Read ORER and FER flags in SSR Yes
FER ORER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
[Legend] : Logical OR
Yes
Read receive data in RDR
No
All data received?
[5] Error processing
Yes
Clear RE bit in SCR to 0
(Continued on next page)

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 12 Serial Communication Interface (SCI and IrDA)
[5]
Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
Clear ORER, PER, and FER flags in SSR to 0

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 12 Serial Communication Interface (SCI and IrDA)
12.6
Operation in Clock Synchronous Mode
Figure 12.14 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer/reception Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 12.14 Data Format in Clock Synchronous Communication (LSB-First) 12.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.
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Section 12 Serial Communication Interface (SCI and IrDA)
12.6.2
SCI Initialization (Clock Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR.
Start initialization
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE to 0. [2] Set the data transfer/receive format in SMR and SCMR.
[1]
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
Set data transfer/receive format in SMR and SCMR Set value in BRR
[2]
[3]
Wait
No 1-bit interval elapsed? Yes
Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[4]

Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 12.15 Sample SCI Initialization Flowchart
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Section 12 Serial Communication Interface (SCI and IrDA)
12.6.3
Serial Data Transmission (Clock Synchronous Mode)
Figure 12.16 shows an example of SCI operation for transmission in clock synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 12.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.
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Section 12 Serial Communication Interface (SCI and IrDA)
Transfer direction
Synchronization clock
Serial data
TDRE TEND TXI interrupt request generated
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine 1 frame
TXI interrupt request generated
TEI interrupt request generated
Figure 12.16 Example of SCI Transmit Operation in Clock Synchronous Mode
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start transmission
[1]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0.
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
Figure 12.17 Sample Serial Transmission Flowchart
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Section 12 Serial Communication Interface (SCI and IrDA)
12.6.4
Serial Data Reception (Clock Synchronous Mode)
Figure 12.18 shows an example of SCI operation for reception in clock synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Synchronization clock
Serial data
RDRF ORER
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RXI interrupt request generated
RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine 1 frame
RXI interrupt request generated
ERI interrupt request generated by overrun error
Figure 12.18 Example of SCI Receive Operation in Clock Synchronous Mode
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Section 12 Serial Communication Interface (SCI and IrDA)
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart for serial data reception.
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished.
Read ORER flag in SSR
[2]
Yes
ORER = 1
[3] Error processing (Continued below)
No
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR and clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear RE bit in SCR to 0

[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0

Figure 12.19 Sample Serial Reception Flowchart
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Section 12 Serial Communication Interface (SCI and IrDA)
12.6.5
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, check that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0, and then set the TE and RE bits to 1 simultaneously with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, check that the SCI has finished reception, and clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, set the TE and RE bits to 1 simultaneously with a single instruction.
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Section 12 Serial Communication Interface (SCI and IrDA)
Initialization Start transmission/reception
[1]
[1]
SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt.
Read TDRE flag in SSR No
TDRE = 1
[2]
[2]
Yes
Write transmit data to TDR and clear TDRE flag in SSR to 0
[3]
Read ORER flag in SSR
ORER = 1
Yes
[3] Error processing
No
[4]
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR, and clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
[5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0.

Note: * When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
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Section 12 Serial Communication Interface (SCI and IrDA)
12.7
IrDA Operation
IrDA operation can be used with SCI_2. Figure 12.21 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in KBCOMP, the TxD2 and RxD2 pins in SCI_2 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming.
IrDA SCI_2
TxD2/IrTxD
Pulse encoder
TxD
RxD2/IrRxD
Pulse decoder
RxD
KBCOMP
Figure 12.21 IrDA Block Diagram
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Section 12 Serial Communication Interface (SCI and IrDA)
Transmission: During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 12.22). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in KBCOMP. The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s at maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of at least 1.4 s to 1.6 s can be specified. For serial data of level 1, no pulses are output.
UART frame
Start bit
Data
Stop bit
0
1
0
1
0
0
1
1
0
1
Transmission
Reception
IR frame
Start bit
Data
Stop bit
0
1
0
1
0
0
1
1
0
1
Bit cycle
Pulse width is 1.6 s to 3/16 bit cycle
Figure 12.22 IrDA Transmission and Reception Reception: During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI_2. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is recognized as level 0.
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Section 12 Serial Communication Interface (SCI and IrDA)
High-Level Pulse Width Selection: Table 12.10 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 12.10 IrCKS2 to IrCKS0 Bit Settings
Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 57600 3.26 010 010 010 011 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 115200 1.63 -- -- -- -- 011 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101
[Legend] --: An SCI bit rate setting cannot be made.
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Section 12 Serial Communication Interface (SCI and IrDA)
12.8
Interrupt Sources
Table 12.11 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 12.11 SCI Interrupt Sources
Channel 0 Name ERI0 RXI0 TXI0 TEI0 1 ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND Low Priority High
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Section 12 Serial Communication Interface (SCI and IrDA)
12.9
12.9.1
Usage Notes
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 18, Power-Down Modes. 12.9.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 12.9.3 Mark State and Break Detection
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 12.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 12.9.5 Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1.
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Section 12 Serial Communication Interface (SCI and IrDA)
12.9.6
SCI Operations during Mode Transitions
Transmission: Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If a transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 12.23 shows a sample flowchart for mode transition during transmission. Figures 12.24 and 12.25 show the pin states during transmission. Reception: Before making a transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 12.27 shows a sample flowchart for mode transition during reception.
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Section 12 Serial Communication Interface (SCI and IrDA)
Transmission
All data transmitted?
No
[1]
Yes
Read TEND flag in SSR
[1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after a mode is released. [2] Also clear TIE and TEIE to 0 when they are 1. [3] Module stop, watch, sub-active, and sub-sleep modes are included.
TEND = 1
No
Yes
TE = 0
[2] [3]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
No
Yes
Initialization
TE = 1
Start transmission
Figure 12.23 Sample Flowchart for Mode Transition during Transmission
Transition to Software standby Transmission end software standby mode cancelled mode
Transmission start
TE bit SCK output pin TxD output pin
Port input/output Port input/output
High output
Start SCI TxD output
Stop
Port input/output Port
High output SCI TxD output
Port
Figure 12.24 Pin States during Transmission in Asynchronous Mode (Internal Clock)
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Section 12 Serial Communication Interface (SCI and IrDA)
Transmission start
Transmission end
Transition to Software standby software standby mode cancelled mode
TE bit SCK output pin
TxD output pin
Port input/output
Port input/output
Marking output
SCI TxD output
Last TxD bit retained
Port input/output
Port
High output*
SCI TxD output
Port Note:* Initialized in software standby mode
Figure 12.25 Pin States during Transmission in Clock Synchronous Mode (Internal Clock)
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Section 12 Serial Communication Interface (SCI and IrDA)
Reception
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Data being received will be invalid.
Yes
Read receive data in RDR
[2] Module stop, watch, sub-active, and subsleep modes are included.
RE = 0
[2]
Make transition to software standby mode etc.
Cancel software standby mode etc.
Change operating mode?
No
Yes
Initialization
RE = 1
Start reception
Figure 12.26 Sample Flowchart for Mode Transition during Reception
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Section 12 Serial Communication Interface (SCI and IrDA)
12.9.7
Notes on Switching from SCK Pins to Port Pins
When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 12.28.
Low pulse of half a cycle
SCK/Port
1. Transmission end Data
Bit 6
Bit 7
4. Low pulse output
TE C/A CKE1 CKE0
2. TE = 0 3. C/A = 0
Figure 12.27 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1. 1. 2. 3. 4. 5. End serial data transmission TE bit = 0 CKE1 bit = 1 C/A bit = 0 (switch to port output) CKE1 bit = 0
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Section 12 Serial Communication Interface (SCI and IrDA)
High output
SCK/Port
1. Transmission end Data
Bit 6
Bit 7
TE C/A
2. TE = 0 4. C/A = 0 3. CKE1 = 1
5. CKE1 = 0
CKE1 CKE0
Figure 12.28 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
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Section 13 D/A Converter
Section 13 D/A Converter
13.1
* * * * *
Features
8-bit resolution Two output channels Conversion time: Max. 10 s (when load capacitance is 20 pF) Output voltage: 0 V to AVref for the H8S/2144B and 0 V to AVcc for the H8S/2134B D/A output retaining function in software standby mode
Module data bus
Internal data bus
AVref* AVCC
DADR0
DADR1
DA1 DA0 AVSS
8-bit D/A
Control circuit
[Legend] DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1
Note: * Available only for the H8S/2144B.
Figure 13.1 Block Diagram of D/A Converter
DAC0002A_010020020700
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DACR
Bus interface
Section 13 D/A Converter
13.2
Input/Output Pins
Table 13.1 summarizes the input/output pins used by the D/A converter. Table 13.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Note: * Symbol AVCC AVSS DA0 DA1 I/O Input Input Output Output Input Function Analog block power supply Analog block ground and reference voltage Channel 0 analog output Channel 1 analog output Analog block reference voltage
Reference power supply pin AVref*
Available only for the H8S/2144B.
13.3
Register Descriptions
The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 13.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1)
DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When analog output is permitted, D/A data register contents are converted and output to analog output pins. DADR0 and DADR1 are initialized to H00.
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Section 13 D/A Converter
13.3.2
D/A Control Register (DACR)
DACR controls D/A converter operation.
Bit 7 Bit Name DAOE1 Initial Value 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output DA0 is disabled 1: D/A conversion for channel 0 and analog output DA0 are enabled 5 DAE 0 R/W D/A Enable Controls D/A conversion in conjunction with the DAOE0 and DAOE1 bits. When the DAE bit is cleared to 0, D/A conversion for channels 0 and 1 is controlled individually. When the DAE bit is set to 1, D/A conversion for channels 0 and 1 are controlled as one. Conversion result output is controlled by the DAOE0 and DAOE1 bits. For details, see table 13.2 below. 4 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified.
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Section 13 D/A Converter
Table 13.2 D/A Channel Enable
Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE -- 0 1 1 0 0 1 1 -- Description Disables D/A conversion Enables D/A conversion for channel 0 Disables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Disables D/A conversion for channel 0 Enables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Enables D/A conversion for channels 0 and 1
13.4
Operation
The D/A converter incorporates two channels of the D/A circuits and can be converted individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 13.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV, conversion results are output from the analog output pin DA0. The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. The output value is calculated by the following formula:
DADR contents/256 x AVref
3. Conversion starts immediately after DADR0 is modified. After the interval of tDCONV, conversion results are output. 4. When the DAOE0 bit is cleared to 0, analog output is disabled.
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Section 13 D/A Converter
DADR0 write cycle
DACR write cycle
DADR0 write cycle
DACR write cycle
Address
DADR0
Conversion data (1)
Conversion data (2)
DAOE0 Conversion result (2) tDCONV
DA0 High impedance state
tDCONV
Conversion result (1)
[Legend] tDCONV: D/A conversion time
Figure 13.2 D/A Converter Operation Example
13.5
Usage Note
When this LSI enters software standby mode with D/A conversion enabled, the D/A output is retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0, and DAE bits all to 0 to disable D/A output. 13.5.1 Module Stop Mode Setting
D/A converter operation can be enabled or disabled using the module stop control register. The initial setting is for D/A converter operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 18, Power-Down Modes.
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Section 13 D/A Converter
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Section 14 A/D Converter
Section 14 A/D Converter
This LSI includes a 10-bit successive-approximation-type A/D converter that allows up to eight analog input channels and up to 16 digital input channels* to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. Note: * Up to eight channels in the H8S/2134B
14.1
Features
* 10-bit resolution * Input channels: eight analog input channels and 16 digital input channels*1 * Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref*2) as an analog reference voltage. * Conversion time: 13.4 s per channel (at 10-MHz operation) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Software, 8-bit timer (TMR) conversion start trigger, or external trigger signal. * Interrupt request A/D conversion end interrupt (ADI) request can be generated Notes: 1. Up to eight channels in the H8S/2134B 2. Available only for the H8S/2144B.
ADCMS33A_010020020700
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Section 14 A/D Converter
A block diagram of the A/D converter is shown in figure 14.1.
Module data bus
Internal data bus
Bus interface
Successive approximations register
AVCC AVref* AVSS
10-bit D/A
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN0 AN1 AN2 AN3 AN4 AN5 AN6/CIN0 to CIN7 AN7/CIN8 to CIN15*
Multiplexer
+
/8
Comparator Sample-and-hold circuit
Control circuit /16
ADI interrupt signal
Conversion start trigger from 8-bit timer
ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD:
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Note: * Available only for the H8S/2144B.
Figure 14.1 Block Diagram of A/D Converter
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Section 14 A/D Converter
14.2
Input/Output Pins
Table 14.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. Expanded A/D conversion input pins (CIN0 to CIN15) can be selected with the AN6 and AN7 pins. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 14.1 Pin Configuration
Pin Name Symbol I/O Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Expanded A/D conversion input (digital input) channels 0 to 15. Can be used as digital input pins. Channels 0 to 7 are available for the H8S/2134B. Group 1 analog input pins Function Analog block power supply and reference voltage Analog block ground and reference voltage Reference voltage for A/D conversion (Available only for the H8S/2144B.) Group 0 analog input pins
Analog power supply AVCC pin Analog ground pin Reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin AVSS AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG
Expanded A/D CIN0 to conversion input pins CIN15 0 to 15
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Section 14 A/D Converter
14.3
Register Descriptions
The A/D converter has the following registers. * * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) Keyboard comparator control register (KBCOMP) A/D Data Registers A to D (ADDRA to ADDRD)
14.3.1
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 14.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read directly from the CPU, but the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before lower byte or in word units. Table 14.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel Group 0 AN0 An1 AN2 AN3 Note: * Group 1 AN4 AN5 AN6, or CIN0 to CIN7 AN7, or CIN8 to CIN15* Available only for the H8S/2144B. A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD
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Section 14 A/D Converter
14.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)*
1
Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode When 0 is written after reading ADF = 1
[Clearing conditions] * 6 5 ADIE ADST 0 0 R/W R/W A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1 A/D Start Setting this bit to 1 starts A/D conversion. Clearing this bit to 0 stops A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects the A/D conversion operating mode. The setting of this bit must be made when conversion is halted (ADST = 0). 0: Single mode 1: Scan mode 3 CKS 0 R/W Clock Select Sets A/D conversion time. The input channel setting must be made when conversion is halted (ADST = 0). 0: Conversion time is 266 states (max) 1: Conversion time is 134 states (max) Switch conversion time while ADST is 0.
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Section 14 A/D Converter
Bit 2 1 0
Bit Name CH2 CH1 CH0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Channel Select 2 to 0 Select analog input channels. The input channel setting must be made when conversion is halted (ADST = 0). When SCAN = 0: 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 When SCAN = 1: 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5
110: AN6, or CIN0 to CIN7 110: AN4 to AN6 or CIN0 to CIN7 111: AN7, or CIN8 to CIN15*
2
111: AN4 to AN6 or CIN0 to CIN7, or AN7 or CIN8 to 2 CIN15*
Notes: 1. Only 0 can be written for clearing the flag. 2. CIN8 to CIN15 are available only for the H8S/2144B.
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Section 14 A/D Converter
14.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 Enable the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 when conversion is halted (ADST = 0). 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger is disabled 10: A/D conversion start by conversion trigger from TMR is enabled 11: A/D conversion start by ADTRG pin is enabled 5 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified.
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Section 14 A/D Converter
14.3.4
Keyboard Comparator Control Register (KBCOMP)
KBCOMP selects the CIN input channel for which A/D conversion is performed and enables or disables the comparator scan function of CIN15 to CIN0.
Bit 7 6 5 4 3 Bit Name IrE IrCKS2 IrCKS1 IrCKS0 KBADE Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Keyboard A/D Enable (AN6, AN7) Selects whether channels 6 and 7 of the A/D converter are used as analog pins or digital pins, in combination with the KBCH2 to KBCH0 bits. For details, refer to description for bits 2 to 0. Analog pins of the A/D converter are set to digital pins (CIN0 to CIN7 and CIN8 to CIN15*). 2 1 0 KBCH2 KBCH1 KBCH0 0 0 0 R/W R/W R/W Keyboard A/D Channel Select 2 to 0 These bits select a channel of digital input pins for A/D conversion, in combination with the KBADE bit. The input channel setting must be made while conversion is halted. Channel 6 0xxx: Selects AN6 1000: Selects CIN0 1001: Selects CIN1 1010: Selects CIN2 1011: Selects CIN3 1100: Selects CIN4 1101: Selects CIN5 1110: Selects CIN6 1111: Selects CIN7 [Legend] x: Don't care Note: * CIN8 to CIN15 are available only for the H8S/2144B. Channel 7 AN7 CIN8* CIN9* CIN10* CIN11* CIN12* CIN13* CIN14* CIN15* Description These bits are related to the SCI. For details, refer to section 12.3.10, Keyboard Comparator Control Register (KBCOMP).
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Section 14 A/D Converter
14.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 14.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1, by software or an external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0, and the A/D converter enters wait state. 14.4.2 Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described below.
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Section 14 A/D Converter
Figure 14.2 shows the operation timing. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
Continuous A/D conversion execution
Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle
A/D conversion 1
Clear*1 Clear*1
Idle
A/D conversion 2
A/D conversion 4
Idle
A/D conversion 5 *2
Idle
A/D conversion 3
Idle Idle
Idle
Figure 14.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
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Section 14 A/D Converter
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 14.3 shows the A/D conversion timing. Table 14.3 indicates the A/D conversion time. As indicated in figure 14.3, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14.3. In scan mode, the values given in table 14.3 apply to the first conversion time. In the second and subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states (fixed) when CKS = 1.
(1)
Address
(2)
Write signal
Input sampling timing
ADF
tD tSPL
tCONV
[Legend] (1) : ADCSR write cycle (2) : ADCSR address : A/D conversion start delay tD tSPL : Input sampling time tCONV : A/D conversion time
Figure 14.3 A/D Conversion Timing
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Section 14 A/D Converter
Table 14.3 A/D Conversion Time (Single Mode)
CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Note: * Symbol tD tSPL tCONV Min. 10 -- 259 Typ. -- 63 -- Max. 17 -- 266 Min. 6 -- 131 CKS = 1 Typ. -- 31 -- Max. 9 -- 134
Values in the table indicate the number of states.
14.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 14.4 shows the timing.
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 14.4 External Trigger Input Timing
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Section 14 A/D Converter
14.5
Interrupt Sources
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion is completed.
14.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.5). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 14.6). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 14.6). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 14.6). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.
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Section 14 A/D Converter
Digital output
H'3FF H'3FE H'3FD H'004 H'003 H'002
Ideal A/D conversion characteristic
Quantization error
H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage
Figure 14.5 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic
FS
Offset error
Analog input voltage
Figure 14.6 A/D Conversion Accuracy Definitions
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Section 14 A/D Converter
14.7
14.7.1
Usage Notes
Permissible Signal Source Impedance
Analog inputs of this LSI are designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/s or greater) (see figure 14.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. For details on the 5-V version, refer to section 20, Electrical Characteristics. 14.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with ground, and therefore noise in ground may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable ground such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas.
This LSI Sensor output impedance to 5 k
Sensor input
Cin = 15 pF
A/D converter equivalent circuit
10 k
Low-pass filter C to 0.1 F
20 pF
Figure 14.7 Example of Analog Input Circuit
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Section 14 A/D Converter
14.7.3
Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of this LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the following range. AVss ANn AVref* for the H8S/2144B (n = 0 to 7) Note: * AVref is available only for the H8S/2144B. AVss ANn AVcc for the H8S/2134B (n = 0 to 7). * Digital input voltage range The voltage applied to digital input pin CINn should be in the following range. AVss CINn AVref* and Vss CINn Vcc for the H8S/2144B (n = 0 to 15) Note: * AVref is available only for the H8S/2144B. AVss CINn AVcc and Vss CINn Vcc for the H8S/2134B (n = 0 to 7) * Relation between AVcc, AVss and Vcc, Vss For the relationship between AVcc, AVss and Vcc, Vss, set AVss = Vss. If the A/D converter is not used, the AVcc and AVss pins must on no account be left open. * AVref* pin reference voltage specification range The reference voltage of the AVref* pin should be in the range AVref* AVcc. Note: * AVref is available only for the H8S/2144B. 14.7.4 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference voltage (AVref*), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. Note: * AVref is available only for the H8S/2144B.
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Section 14 A/D Converter
14.7.5
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference voltage (AVref*) should be connected between AVcc and AVss as shown in figure 14.8. Also, the bypass capacitors connected to AVcc and AVref*, and the filter capacitor connected to AN2 to AN7, must be connected to AVSS. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Note: * AVref is available only for the H8S/2144B.
AVCC
AVref (Only for the H8S/2144B)
*1
*1
Rin *2
100 W
AN0 to AN7
0.1 F
AVSS
Notes: Values are reference values.
1.
10 F
0.01 F
2. Rin: Input impedance
Figure 14.8 Example of Analog Input Protection Circuit
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Section 14 A/D Converter
10 k AN0 to AN7 20 pF
To A/D converter
Note:* Values are reference values.
Figure 14.9 Equivalent Circuit of Analog Input Pin 14.7.6 Module Stop Mode Setting
A/D converter operation can be enabled or disabled using the module stop control register. The initial setting is for A/D converter operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 18, Power-Down Modes.
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Section 15 RAM
Section 15 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Product Classification Flash memory version H8S/2144B H8S/2134B RAM Capacitance 4 kbytes 4 kbytes RAM Address H'E080 to H'EFFF, H'FF00 to H'FF7F H'E080 to H'EFFF, H'FF00 to H'FF7F
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Section 15 RAM
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Section 16 ROM
Section 16 ROM
This LSI has an on-chip ROM (flash memory or masked ROM). The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 16.1.
16.1
* Size
Features
Product Classification H8S/2144B H8S/2134B
RAM Capacitance 128 kbytes 128 kbytes
ROM Address H'000000 to H'01FFFF (mode 2) H'0000 to H'DFFF (mode 3) H'000000 to H'01FFFF (mode 2) H'0000 to H'DFFF (mode 3)
* Programming/erasing methods The flash memory is programmed 128 bytes at a time. Erasure is performed in single-block units. The flash memory is configured as follows: 32 kbytes x 2 blocks, 8 kbytes x 2 blocks, 16 kbytes x 1 block, 28 kbytes x 1 block, and 1 kbyte x 4 blocks To erase the entire flash memory, each block must be erased in turn. * Programming/erasing time It takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 s (typ.) per 1 byte. Erasing one block takes 100 ms (typ.). * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Two flash memory on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode in which the boot program built into the chip is started for erasure or programming of the entire flash memory. In user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host.
ROMF254A_010020020700
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Section 16 ROM
* Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. * Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a PROM programmer.
Internal address bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
Module bus
EBR1
EBR2
Bus interface/controller
Operating mode
Mode pin
Flash memory (128 kbytes)
[Legend] FLMCR1: FLMCR2: EBR1: EBR2:
Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2
Figure 16.1 Block Diagram of Flash Memory
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Section 16 ROM
16.2
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 16.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 16.1. Figure 16.3 shows the boot mode and figure 16.4 shows the user program mode.
= MD1
1
=0
Reset state
User mode (on-chip ROM enabled)
RES
RES = 0
*2
=
FLSHE = 1 SWE = 1
*1
RES = 0
RE S
FLSHE = 0 SWE = 0
0
Programmer mode
User program mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. MD1 = MD0 = 0, P92 = P91 = P90 = 1 2. MD1 = MD0 = 0, P92 = 0, P91 = P90 = 1
Boot mode On-board programming mode
Figure 16.2 Flash Memory State Transitions Table 16.1 Differences between Boot Mode and User Program Mode
Boot Mode Total erasure Block erasure Yes No User Program Mode Yes Yes Programming/programmingverifying Erasing/erasing-verifying Note: * Should be provided by the user, in accordance with the recommended algorithm.
Programming control program* Programming/programmingverifying
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Section 16 ROM
1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. Programming control program New application program Boot program
SCI
2. SCI communication check When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and SCI communication is checked. Then the boot program required for flash memory erasing is automatically transferred to the RAM boot program area.
New application program Boot program
SCI
Boot program area Application program (old version) Application program (old version) Programming control program
3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks.
4. Programming new application program The programming control program transferred from the host to RAM via SCI communication is executed, and the new application program in the host is written into the flash memory.
New application program Boot program
SCI
Boot program New application program
SCI
Boot program area Flash memory erase Programming control program
Boot program area Programming control program
Program execution state
Figure 16.3 Boot Mode
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Section 16 ROM
1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory.
2. Programming/erase control program transfer The transfer program in the flash memory is executed and the programming/erase control program is transferred to RAM.
Programming/ erase control program
New application program

New application program

Boot program

SCI
Boot program
SCI

Transfer program

Transfer program

Programming/ erase control program
Application program (old version)
Application program (old version)
3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units.
4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks.

New application program

Boot program

SCI
Boot program
SCI

Transfer program

Transfer program

Programming/ erase control program
Programming/ erase control program New application program
Flash memory erase
Program execution state
Figure 16.4 User Program Mode (Example)
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Section 16 ROM
16.3
16.3.1
Block Configuration
Block Configuration
Figure 16.5 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 8 kbytes (2 blocks), 16 kbytes (1 block), 28 kbytes (1 block), and 1 kbyte (4 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80.
EB0 Erase unit: 1 kbyte
H'000000 H'000380
H'000001 H'000381 H'000401
H'000002 H'000382 H'000402
Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes --------------
H'00007F H'0003FF H'00047F H'0007FF H'00087F
EB1 Erase unit: 1 kbyte
H'000400
H'000780 EB2 Erase unit: 1 kbytes H'000800
H'000781 H'000801
H'000782 H'000802
H'000B80 EB3 Erase unit: 1 kbytes H'000F80 EB4 Erase unit: 28 kbytes H'007F80 EB5 Erase unit: 16 kbytes H'00BF80 EB6 Erase unit: 8 kbytes H'00DF80 EB7 Erase unit: 8 kbytes H'00FF80 EB8 Erase unit: 32 kbytes H'017F80 EB9 Erase unit: 32 kbytes H'01FF80 H'018000 H'010000 H'00E000 H'00C000 H'008000 H'001000 H'000C00
H'000B81 H'000C01
H'000B82 H'000C02
H'000BFF H'000C7F H'000FFF H'00107F H'007FFF H'00807F H'00BFFF H'00C07F H'00DFFF H'00E07F
H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001 H'00DF81 H'00E001 H'00FF81 H'010001 H'017F81 H'018001 H'01FF81
H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002 H'00DF82 H'00E002 H'00FF82 H'010002 H'017F82 H'018002 H'01FF82
H'00FFFF H'01007F H'017FFF H'01807F
H'01FFFF
Figure 16.5 Flash Memory Block Configuration
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Section 16 ROM
16.4
Input/Output Pins
The flash memory is controlled by means of the pins shown in table 16.2. Table 16.2 Pin Configuration
Pin Name RES MD1 MD0 P92 P91 P90 TxD1 RxD1 I/O Input Input Input Input Input Input Output Input Function Reset Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Serial transmit data output Serial receive data input
16.5
Register Descriptions
The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2, the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the serial/timer control register, refer to section 3.2.3, Serial/Timer Control Register (STCR). * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Erase block register 2 (EBR2)
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Section 16 ROM
16.5.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1, used together with FLMCR2, makes the flash memory enter the programming mode, programming-verifying mode, erasure mode, or erasure-verifying mode. For details on register setting, refer to section 16.8, Flash Memory Programming/Erasing. FLMCR1 is initialized to H'80 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode.
Bit 7 Bit Name FWE Initial Value 1 R/W R Description Flash Write Enable Controls programming/erasing of on-chip flash memory. This bit is always read as 0, and cannot be modified. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, the EV, PV, E, and P bits in this register, the ESU and PSU bits in FLMCR2, and all EBR1 and EBR2 bits cannot be set to 1. Do not clear these bits and SWE to 0 simultaneously. 5 4 3 -- -- EV 0 0 0 R R R/W Reserved These bits are always read as 0 and cannot be modified. Erasing-Verifying When this bit is set to 1 while SWE = 1, the flash memory transits to erasure-verifying mode. When it is cleared to 0, erasure-verifying mode is cancelled. 2 PV 0 R/W Programming-Verifying When this bit is set to 1 while SWE = 1, the flash memory transits to programming-verifying mode. When it is cleared to 0, programming-verifying mode is cancelled. 1 E 0 R/W Erasure When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory enters the erasing mode. When it is cleared to 0, erasing mode is cancelled.
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Section 16 ROM
Bit 0
Bit Name P
Initial Value 0
R/W R/W
Description Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory enters the programming mode. When it is cleared to 0, programming mode is cancelled.
16.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash memory error Indicates that an error has occurred during flash memory programming/erasing. When this bit is set to 1, flash memory goes to the error-protection state. For details, see section 16.9.3, Error Protection. 6 to 2 -- 1 ESU All 0 0 R/(W) R/W Reserved The initial values should not be modified. Erase Setup When this bit is set to 1 while SWE = 1, the flash memory transits to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit in FLMCR1 to 1. 0 PSU 0 R/W Program Setup When this bit is set to 1 while SWE = 1, the flash memory enters the programming setup state. When it is cleared to 0, the programming setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1 to 1.
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Section 16 ROM
16.5.3
Erase Block Registers 1 and 2 (EBR1, EBR2)
EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0. * EBR1
Bit 7 to 0 Bit Name -- Initial Value All 0 R/W R/(W) Description Reserved The initial values should not be modified.
* EBR2
Bit 7 6 5 4 3 2 1 0 Note: * Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W* R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) are to be erased. When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) are to be erased. When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) are to be erased. When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) are to be erased. When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) is to be erased. When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) is to be erased. When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) is to be erased. When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) is to be erased.
In normal mode, this bit is always read as 0 and cannot be modified.
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Section 16 ROM
16.6
Operating Modes
The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. Note that word data must start from an even address. On-chip ROM is enabled or disabled by the mode select pins (MD1 and MD0) and the EXPE bit in MDCR, as summarized in table 16.3. In normal mode (mode 3), up to 56 kbytes of ROM can be used. Table 16.3 Operating Modes and ROM
Operating Modes MCU CPU Operating Operating Mode Mode Mode 1 Mode 2 Normal Advanced Advanced Mode 3 Normal Normal Mode Pins MDCR
Mode Expanded mode with on-chip ROM disabled Single-chip mode Expanded mode with on-chip ROM enabled Single-chip mode Expanded mode with on-chip ROM enabled
MD1 0 1 1 1 1
MD0 1 0 0 1 1
EXPE 1 0 1 0 1
On-Chip ROM Disabled Enabled (128 kbytes)
Enabled (56 kbytes)
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Section 16 ROM
16.7
On-Board Programming Modes
An on-board programming mode is used to perform on-chip flash memory programming, erasing, and verification. This LSI has two on-board programming modes: boot mode and user program mode. Table 16.4 shows pin settings for boot mode. In user program mode, operation by software is enabled by setting control bits. For details on flash memory mode transitions, see figure 16.2. Table 16.4 On-Board Programming Mode Settings
Mode Setting Boot mode User program mode Note: * Mode 2 (advanced mode) Mode 3 (normal mode) MD1 0 1 1 MD0 0 0 1 P92 1* P91 1* P90 1*
Can be used as an I/O port after the boot mode activation.
16.7.1
Boot Mode
Table 16.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 16.8, Flash Memory Programming/Erasing. In boot mode, if any data exists in the flash memory (except in the case that all data are 1), all blocks in the flash memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery when user program mode cannot be executed because the program to be initiated in user program mode was mistakenly erased. 2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, this LSI measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins should be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states before this LSI is ready to measure the low-level period.
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Section 16 ROM
4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to this LSI. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 16.6. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses H'FFE080 to H'FFE87F is the area to which the programming control program is transferred from the host. Note, however, that ID codes are assigned to addresses H'FFE080 to H'FFE087. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. Figure 16.8 shows the on-chip RAM area in boot mode. 6. Before branching to the programming control program (H'FFE088 in the RAM area), this LSI terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verifying data with the host. The TxD1 pin is in high-level output state. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. Cancel the reset*1 after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the mode pin input levels in boot mode. If mode pin input levels are changed from low to high during reset, operating modes are switched and the state of ports that are also used for address output and bus control output signals (AS, RD, and HWR) are changed*5. Therefore, set these pins carefully not to be output signals during reset or not to conflict with LSI external signals. 9. All interrupts are disabled during programming or erasing of the flash memory. Notes: 1. After a reset is released, the timing for setting the signal levels on mode pins must satisfy the mode programming setup time (tMDS = 4 cycles). 2. The ports that also have address output functions output low as address output when the mode pins are set to mode 1 during a reset. In modes other than mode 1, it enters the high impedance state. Bus control output signals output high when the mode pins are set to mode 1 during a reset. In modes other than mode 1, it enters the high impedance state.
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Section 16 ROM
Table 16.5 Boot Mode Operation
Item
Host Operation Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start.
Boot mode start
Boot program start
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00 H'55
* Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_1. * Transmits data H'00 to host as adjustment end indication.
Receives data H'AA.
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte).
H'AA
After receiving data H'55, transmits data H'AA to host.
Transfer of programming control program
High-order byte and low-order byte Echoback
H'XX
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times).
Echoback
Echobacks received data to host and also transfers it to RAM (repeated for N times).
Flash memory erase
Boot program erase error
H'FF
Receives data H'AA.
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.)
Branches to programming control program transferred to on-chip RAM and starts execution.
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Section 16 ROM
Table 16.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
Host Bit Rate 19200 bps 9600 bps 4800 bps System Clock Frequency Range of This LSI 8 to 20 MHz 4 to 20 MHz 2 to 18 MHz
H'FFE080 ID code area H'FFE088 Programming control program area (2040 bytes) H'FFE880 Boot program area* (1920 bytes)
H'FFEFFF H'FFFF00 Boot program area* (128 bytes) H'FFFF7F Note: The boot program area and area which is not used cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the contents of the boot program area in RAM are remained after a branch is made to the programming control program.
Figure 16.6 On-Chip RAM Area in Boot Mode In boot mode, this LSI checks the contents of the 8-byte ID code area as shown below to confirm that the programming control program corresponds with this LSI. To originally write a programming control program to be used in boot mode, the above 8-byte ID code must be added at the beginning of the program.
H'FFE080
40
FE
64
66
32
31
34
39
H'FFE088
(Product ID) H8S/2144B, H8S/2134B Instruction codes of the programming control program
Figure 16.7 ID Code Area
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Section 16 ROM
16.7.2
User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user programming/erasing control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user programming/erasing control program or a program which provides the user programming/erasing control program from external memory. Because the flash memory itself cannot be read during programming/erasing, transfer the user programming/erasing control program to on-chip RAM, as like in boot mode. Figure 16.10 shows a sample procedure for programming/erasing in user program mode. Prepare a user programming/erasing control program in accordance with the description in section 16.8, Flash Memory Programming/Erasing.
Reset-start
No Program/erase? Yes Transfer user program/ erase control program to RAM Branch to flash memory application program
Branch to user program/ erase control program in RAM
Execute user program/erase control program (flash memory rewrite)
Branch to flash memory application program
Figure 16.8 Programming/Erasing Flowchart Example in User Program Mode
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Section 16 ROM
16.8
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: programming mode, programming-verifying mode, erasing mode, and erasing-verifying mode. The programming control program in boot mode and the user programming/erasing control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 16.8.1, Programming/ProgrammingVerifying and section 16.8.2, Erasing/Erasing-Verifying, respectively. 16.8.1 Programming/Programming-Verifying
When writing data or programs to the flash memory, the programming/programming-verifying flowchart shown in figure 16.11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting this LSI to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 16.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The programming address and 128byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 16.9 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. The overflow cycle should be longer than (y + z2 + + ) s. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words from the address to which a dummy write was performed.
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Section 16 ROM
8. The maximum number of repetitions of the programming/programming-verifying sequence to the same bit is (N).
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Section 16 ROM
Write pulse application subroutine
Start of programming
Sub-Routine Write Pulse
WDT enable
START
Set SWE bit in FLMCR1
Wait (x) s
Store 128-byte program data in program data area and reprogram data area
Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Set PSU bit in FLMCR2
Wait () s
Set P bit in FLMCR1 Wait (z1) s, (z2) s or (z3) s
Clear P bit in FLMCR1 Wait () s
Clear PSU bit in FLMCR2 Wait () s
Disable WDT
*4
n=1
m=0
*5
Write 128-byte data in RAM reprogram data area consecutively to flash memory
*1
Sub-Routine-Call Apply write pulse z1 s or z2 s
Set PV bit in FLMCR1
See Note 7 for pulse width
Wait () s
H'FF dummy write to verify address
Wait () s
nn+1
End Sub
Increment address
Read verify data
*2
NG
m=1
NG
Note 7: Write Pulse Width Number of Writes n Write Time (z) s
Write data = verify data?
1 2 3 4 5 6 7 8 9 10 11 12 13
z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z2 z2
OK
6n?
OK Additional-programming data computation
Transfer additional-programming data to additional-programming data area
Reprogram data computation
*4
*3 *4
Transfer reprogram data to reprogram data area
128-byte data verification completed?
NG
998 999 1000
z2 z2 z2
OK Clear PV bit in FLMCR1
Wait () s
6 n?
Note: Use a z3 s write pulse for additional programming.
NG
RAM
Program data storage area (128 bytes)
OK Successively write 128-byte data from additional1 programming data area in RAM to flash memory *
Apply write pulse (Additional programming)
*3
s
n (N)?
Reprogram data storage area (128 bytes)
m=0?
NG
NG
Additional-programming data storage area (128 bytes)
OK Clear SWE bit in FLMCR1
Wait () s
End of programming
OK Clear SWE bit in FLMCR1
Wait () s
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 6. The values of x, y, z1, z2, z3, , , , , , , and N are shown in section 20.1.6, Flash Memory Characteristics, and section 20.2.6, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data Verify Data Reprogram Data
Additional-Programming Data Computation Table
(D)
0 0 1 1
(V)
0 1 0 1
(X)
1 0 1 1
Comments
Programming completed Programming incomplete; reprogram Still in erased state; no action
Reprogram Data (X') 0 0 1 1
Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1
Comments
Additional programming to be executed Additional programming not to be executed Additional programming not to be executed
Figure 16.9 Programming/Programming-Verifying Flowchart
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Section 16 ROM
16.8.2
Erasing/Erasing-Verifying
When erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 16.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately (y + z + + ) ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is unerased, set erase mode again, and repeat the erasing/erasure-verifying sequence as before. The maximum number of repetitions of the erasing/erasure-verifying sequence is N.
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Section 16 ROM
START
*1
Set SWE bit in FLMCR1
Wait (x) s
n=1
Set EBR1 and EBR2
*2
*4
Enable WDT
Set ESU bit in FLMCR2
Wait (y) s
Set E bit in FLMCR1
*2
Start of erasing
Wait (z) ms
Clear E bit in FLMCR1
*2
End of erasing
Wait () s
Clear ESU bit in FLMCR2
*2
Wait () s
Disable WDT
*2
Set EV bit in FLMCR1
Wait () s
Set block start address as verify address
H'FF dummy write to verify address
*2
nn + 1
Wait () s
Read verify data
Increment address
*2
*3
NG
Verify data = all "1"?
OK NG
Last address of block?
OK Clear EV bit in FLMCR1
Clear EV bit in FLMCR1
Wait () s
Wait () s
*2
NG
*2
n (N) ?
*5
All erase blocks erased?
*2 NG
OK
Clear SWE bit in FLMCR1
OK Clear SWE bit in FLMCR1
Wait () s
Erase failure
Wait () s
End of erasing
Notes:
1. Prewriting (writing 0 to all data in erased block) is not necessary. 2. The values of x, y, z, , , , , , , and N are shown in section 20.1.6, Flash Memory Characteristics, and section 20.2.6, Flash Memory Characteristics. 3. Verify data is read in 16-bit (word) units. 4. Set only a single bit in EBR1 and EBR2. Do not set more than one bit. 5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 16.10 Erasing/Erasing-Verifying Flowchart
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Section 16 ROM
16.9
Programming/Eraseing Protection
There are three kinds of flash memory programming/erasing protection: hardware protection, software protection, and error protection. 16.9.1 Hardware Protection
Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode. Flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and erase block registers 1 and 2 (EBR1 and EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 16.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. 16.9.3 Error Protection
In error protection, an error is detected when the CPU's runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the programming/erasing algorithm, and the programming/erasing operation is aborted. Aborting the programming/erasing operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed (transits to software standby mode, sleep mode, subactive mode, sub-sleep mode, or watch mode) during programming/erasing * When the bus ownership is released during programming/erasing
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Section 16 ROM
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but programming mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to the verifying mode can be made. The error protection state can be cancelled by a reset or in hardware standby mode.
16.10
Interrupts during Flash Memory Programming/Erasing
In order to give the highest priority to programming/erasing operations, disable all interrupts including NMI input during flash memory programming/erasing (the P or E bit in FlMCR1 is set to 1) or boot program execution*1. 1. If an interrupt is generated during programming/erasing, operation in accordance with the programming/erasing algorithm is not guaranteed. 2. CPU runaway may occur because normal vector reading cannot be performed in interrupt exception handling during programming/erasing*2. 3. If an interrupt occurs during boot program execution, the normal boot mode sequence cannot be executed. Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming control program has completed programming. 2. The vector may not be read correctly for the following two reasons: If flash memory is read while being programmed or erased (while the P or E bit in FLMCR1 is set to 1), correct read data will not be obtained (undefined values will be returned). If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly.
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Section 16 ROM
16.11
Programmer Mode
In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports Renesas Technology 128-kbyte flash memory for microcomputer built-in type*. Figure 16.11 shows a memory map in programmer mode. Note: Set the programming voltage of the PROM programmer to 3.3V.
MCU mode H'000000 Programmer mode H'00000
On-chip ROM area
H'01FFFF
H'1FFFF
Figure 16.11 Memory Map in Programmer Mode
16.12
Usage Notes
The following lists notes on the use of on-board programming modes and programmer mode. 1. Perform programming/erasing with the specified voltage and timing. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports Renesas Technology 128-kbyte flash memory for microcomputer built-in type. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. 2. Notes on power on/off At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 3. Perform flash memory programming/erasing in accordance with the recommended algorithm In the recommended algorithm, flash memory programming/erasing can be performed without subjecting this LSI to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1 to 1, set the watchdog timer against program runaway.
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Section 16 ROM
4. Do not set/clear the SWE bit during program execution in the flash memory. Do not set/clear the SWE bit during program execution in the flash memory. An interval of at least 100 s is necessary between program execution or data reading in flash memory and SWE bit clearing. When the SWE bit is set to 1, flash memory data can be modified, however, flash memory data can be read only in programming-verifying or erasing-verifying mode. Do not access the flash memory for a purpose other than verification during programming/erasing. Do not clear the SWE bit during programming, erasing, or verifying. 5. Do not use interrupts during flash memory programming/erasing In order to give the highest priority to programming/erasing operation, disable all interrupts including NMI input when the flash memory is programmed or erased. 6. Do not perform additional programming. Programming must be performed in the erased state. Program the area with 128-byte programming-unit blocks in on-board programming or programmer mode only once. Perform programming in the state where the programming-unit block is fully erased. 7. Ensure that the PROM programmer is correctly attached before programming. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 8. Do not touch the socket adapter or LSI while programming. Touching either of these can cause contact faults and write errors.
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Section 16 ROM
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Section 17 Clock Pulse Generator
Section 17 Clock Pulse Generator
This LSI incorporates a clock pulse generator, which generates the system clock (), bus master clock, and internal clock. The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. Figure 17.1 shows a block diagram of the clock pulse generator.
EXTAL
Oscillator
XTAL
Duty correction circuit Clock select circuit
SUB
Mediumspeed clock divider
/2 to /32
Bus master clock select circuit
EXCL
Subclock input circuit
Waveform forming circuit
System clock to pin WDT_1 count clock
Internal clock to peripheral modules
Bus master clock to CPU
Figure 17.1 Block Diagram of Clock Pulse Generator The bus master clock is selected as either high-speed mode or medium-speed mode by software according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on the standby control register, refer to section 18.1.1, Standby Control Register (SBYCR). The subclock input is controlled by software according to the EXCLE bit setting in the low power control register. For details on the low power control register, refer to section 18.1.2, Low Power Control Register (LPWRCR).
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Section 17 Clock Pulse Generator
17.1
Oscillator
Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 17.1.1 Connecting Crystal Resonator
Figure 17.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 17.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 17.3 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 17.2 should be used. A crystal resonator with frequency identical to that of the system clock () should be used.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF
Figure 17.2 Typical Connection to Crystal Resonator Table 17.1 Damping Resistance Values
Frequency (MHz) Rd () 2 1k 4 500 8 200 10 0 12 0 16 0 20 0
CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator
C0
Figure 17.3 Equivalent Circuit of Crystal Resonator
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Section 17 Clock Pulse Generator
Table 17.2 Crystal Resonator Parameters
Frequency (MHz) RS (max) () C0 (max) (pF) 2 500 4 120 8 80 10 70 7 12 60 16 50 20 40
17.1.2
External Clock Input Method
Figure 17.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 17.3. The frequency of the external clock should be the same as that of the system clock ().
EXTAL XTAL Open
External clock input
(a) Example of external clock input when XTAL pin left open
EXTAL XTAL
External clock input
(b) Example of external clock input when an inverted clock is input to XTAL pin
Figure 17.4 Example of External Clock Input
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Section 17 Clock Pulse Generator
Table 17.3 External Clock Input Conditions
VCC = 4.0 to VCC = 5.0 V 5.5 V 10 % Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Symbol tEXL tEXH tEXr tEXf Min. Max. Min. 25 25 -- -- 0.4 80 Clock pulse width high level tCH 0.4 80 -- -- 5 5 0.6 -- 0.6 -- 20 20 -- -- 0.4 80 0.4 80 Max. Unit -- -- 5 5 0.6 -- 0.6 -- ns ns ns ns tcyc ns tcyc ns 5 MHz < 5 MHz 5 MHz < 5 MHz Figure 20.4 Test Conditions Figure 17.5
Clock pulse width low level tCL
tEXH
tEXL
EXTAL
VCC x 0.5
tEXr
tEXf
Figure 17.5 External Clock Input Timing The oscillator and duty correction circuit have a function to adjust the waveform of the external clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to hold it in reset state. Table 17.4 shows the external clock output stabilization delay time. Figure 17.6 shows the timing of the external clock output stabilization delay time.
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Section 17 Clock Pulse Generator
Table 17.4 External Clock Output Stabilization Delay Time Condition: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V
Item Symbol Min. 500 Max. -- Unit s Remarks Figure 17.6
External clock output stabilization delay tDEXT* time Note: * tDEXT includes a RES pulse width (tRESW).
VCC
2.7 V
STBY
VIH
EXTAL
(Internal and external)
RES tDEXT*
Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW).
Figure 17.6 Timing of External Clock Output Stabilization Delay Time
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Section 17 Clock Pulse Generator
17.2
Duty Correction Circuit
The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects the duty of a clock that is output from the oscillator, and generates the system clock ().
17.3
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (), and generates /2, /4, /8, /16, and /32 clocks.
17.4
Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system clock () or medium-speed clock (/2, /4, /8, /16, or /32) by the SCK2 to SCK0 bits in SBYCR.
17.5
Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. Subclock input conditions are shown in table 17.5. When the subclock is not used, subclock input should not be enabled. Table 17.5 Subclock Input Conditions
Vcc = 4.0 to 5.5 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min. -- -- -- -- Typ. 15.26 15.26 -- -- Max. -- -- 10 10 Unit s s ns ns Measurement Condition Figure 17.7
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Section 17 Clock Pulse Generator
tEXCLH
tEXCLL
EXCL
VCC x 0.5
tEXCLr
tEXCLf
Figure 17.7 Subclock Input Timing
17.6
Subclock Waveform Forming Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
17.7
Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, ports, and interrupt controller and their functions operate depending on the SUB. The count clock and sampling clock for each timer are divided SUB clocks.
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Section 17 Clock Pulse Generator
17.8
17.8.1
Usage Notes
Note on Resonator
Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillator pins does not exceed the maximum rating. 17.8.2 Notes on Board Design
When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit to prevent inductive interference with the correct oscillation as shown in figure 17.8.
Avoid
Signal A Signal B CL2 This LSI
XTAL EXTAL
CL1
Figure 17.8 Note on Board Design of Oscillator Circuit Section
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Section 18 Power-Down Modes
Section 18 Power-Down Modes
For operating modes after the reset state is released, this LSI has not only the normal program execution state but also seven power-down modes in which power dissipation is significantly reduced. In addition, there is also module stop mode in which reduced power dissipation can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16,or /32. * Subactive mode The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Subsleep mode The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 stop operating. * Watch mode The CPU and on-chip peripheral modules other than WDT_1 stop operating. * Software standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating. * Hardware standby mode Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually.
18.1
Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * * * * Standby control register (SBYCR) Low power control register (LPWRCR) Module stop control register H (MSTPCRH) Module stop control register L (MSTPCRL)
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Section 18 Power-Down Modes
18.1.1
Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit 7 Initial Bit Name Value SSBY 0 R/W R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode, subactive mode, or watch mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode 1: Shifts to watch mode or high-speed mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Selects the wait time for clock stabilization from clock oscillation start when canceling software standby mode, watch mode, or subactive mode. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 18.1 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, there are no specific wait requirements. Normally the minimum value is recommended. 3 0 R Reserved This bit is always read as 0, and cannot be modified.
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Section 18 Power-Down Modes
Bit 2 1 0
Initial Bit Name Value SCK2 SCK1 SCK0 0 0 0
R/W R/W R/W R/W
Description System Clock Select 2 to 0 Selects a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, SCK2 to SCK0 must be cleared to 0. 000: High-speed mode 001: Medium-speed clock: /2 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11X: --
Legend X: Don't care
Table 18.1 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time
20 MHz 10 MHz 8 MHz 0.4 0.8 2.0 4.1 0.8 1.6 3.3 6.6 13.1 26.2 1.6 1.0 2.0 4.1 8.2 16.4 32.8 2.0
6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 2.7
4 MHz 20. 4.1 8.2 16.4 32.8 65.6 4.0
2 MHz 4.1 8.2 16.4 32.8 65.5 131.2 8.0
Unit ms
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
8192 states 16384 states 32768 states 65536 states
131072 states 8.2 262144 states 16.4 Reserved 16 states* 0.8
s
Shaded cells indicate the recommended specification. Note: * This setting cannot be made in the flash-memory version of this LSI.
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Section 18 Power-Down Modes
18.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit 7 Initial Bit Name Value DTON 0 R/W R/W Description Direct Transfer On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts directly to subactive mode, or shifts to sleep mode or software standby mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode or watch mode 1: Shifts directly to high-speed mode, or shifts to subsleep mode 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is released. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts to watch mode or subactive mode When the SLEEP instruction is executed in subactive mode: 0: Shifts directly to watch mode or high-speed mode 1: Shifts to subsleep mode or watch mode When watch mode is released: 0: Shifts to high-speed mode 1: Shifts to subactive mode
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Section 18 Power-Down Modes
Bit 5
Initial Bit Name Value NESEL 0
R/W R/W
Description Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL pin is sampled using the clock () generated by the system clock pulse generator. Clear this bit to 0 when is 5 MHz or more. 0: Sampling using /32 clock 1: Sampling using /4 clock
4
EXCLE
0
R/W
Subclock Input Enable Enables/disables subclock input from the EXCL pin. 0: Disables subclock input from the EXCL pin 1: Enables subclock input from the EXCL pin
3
0
R/W
Reserved An undefined value is read from this bit. This bit should not be set to 1.
2 to 0
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
18.1.3
Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH
Bit 7 6 5 4 3 2 1 0 Note: Initial Bit Name Value MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 * 0* 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module 16-bit free-running timer (FRT) 8-bit timers (TMR_0, TMR_1) 14-bit PWM timer (PWMX) D/A converter A/D converter 8-bit timer (TMR_Y)
Do not set this bit to 1.
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Section 18 Power-Down Modes
* MSTPCRL
Bit 7 6 5 4 3 2 Initial Bit Name Value MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Corresponding Module Serial communication interface_0 (SCI_0) Serial communication interface_1 (SCI_1) Serial communication interface_2 (SCI_2) Keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask register A (KMIMRA), port 6 pull-up MOS control register (KMPCR)
1 0 Note:
MSTP1 MSTP0 *
1* 1
R/W R/W
This bit can be read from or written to, however, operation is not affected.
18.2
Mode Transitions and LSI States
Figure 18.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 18.2 shows the LSI internal states in each operating mode.
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Section 18 Power-Down Modes
Program halt state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY = 0, LSON = 0 SLEEP instruction High-speed mode (main clock) Any interrupt SLEEP instruction External interrupt *3 SLEEP instruction Interrupt *1 LSON bit = 0 SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception handling SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception handling SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SSBY = 1, PSS = 0, LSON = 0 Software standby mode Sleep mode (main clock) Hardware standby mode
SCK2 to SCK0 are 0
SCK2 to SCK0 are not 0
Medium-speed mode (main clock)
SLEEP instruction
Interrupt *1 LSON bit = 1 SLEEP instruction Interrupt *2
SSBY = 0, PSS = 1, LSON = 1 Subsleep mode (subclock)
Subactive mode (subclock)
: Transition after exception processing Notes: 1. NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts 2. NMI, IRQ0 to IRQ7, WDT0, WDT1, TMR0, and TMR1 interrupts 3. NMI, IRQ0 to IRQ2, IRQ6, and IRQ7 interrupts
: Power-down mode
* When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * Always select high-speed mode before making a transition to watch mode or sub-active mode.
Figure 18.1 Mode Transition Diagram
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Section 18 Power-Down Modes
Table 18.2 LSI Internal States in Each Mode
Function
System clock pulse generator Subclock pulse generator CPU Instruction execution Registers External interrupts NMI IRQ0 to IRQ7 KIN0 to KIN15 Peripheral WDT_1 modules WDT_0 TMR_0, TMR_1 FRT TMR_Y SCI_0 SCI_1 SCI_2 PWMX D/A converter A/D converter RAM I/O Functioning Retained Functioning Retained Functioning Retained Retained High impedance Function- Halted ing/Halted (reset) (reset) Functioning/Halted (retained) Functioning Function- Functioning ing Functioning Subclock operation Halted (retained) Subclock operation Subclock operation Halted (retained) Halted (reset) Functioning
HighSpeed
Functioning Functioning Functioning
MediumSleep Speed
Function- Functioning ing Function- Functioning ing Medium- Halted speed operation Retained Function- Functioning ing
Module Stop
Functioning Functioning Functioning
Watch
Halted
SubActive
Halted
SubSleep
Halted
Software Hardware Standby Standby
Halted Halted
Functioning Halted
Functioning Subclock operation
Functioning Halted
Halted
Halted
Halted
Halted
Retained Functioning Functioning Functioning
Retained Functioning
Retained Functioning
Undefined Halted
Halted (retained) Halted (reset)
Halted (retained) Halted (reset) Halted (reset)
Note:
*
"Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
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Section 18 Power-Down Modes
18.3
Medium-Speed Mode
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32). On-chip peripheral modules other than the bus masters always operate on the system clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0, operation shifts to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is released, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, medium-speed mode is released and a transition is made to hardware standby mode. Figure 18.2 shows an example of medium-speed mode timing.
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Section 18 Power-Down Modes
Medium-speed mode
, peripheral module clock
Bus master clock
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 18.2 Medium-Speed Mode Timing
18.4
Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU's internal registers are retained. Sleep mode is exited by any interrupt, the RES pin, or the STBY pin. When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation stabilization time has passed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin level is driven low, sleep mode is released and a transition is made to hardware standby mode.
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Section 18 Power-Down Modes
18.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT_1) is cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of I/O ports and on-chip peripheral modules other than the SCI and PWMX are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), the RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2, IRQ6, and IRQ7 is generated. Software standby mode cannot be cleared if an interrupt enable bit corresponding to an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt is cleared to 0 or if the interrupt has been masked on the CPU side. When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation stabilizes, the CPU begins reset exception handling. When the STBY pin is driven low, software standby mode is released and a transition is made to hardware standby mode. Figure 18.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin.
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Section 18 Power-Down Modes
Oscillator
NMI
NMIEG
SSBY
NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction
Oscillation stabilization time tOSC2
NMI exception handling
Figure 18.3 Application Example in Software Standby Mode
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Section 18 Power-Down Modes
18.6
Hardware Standby Mode
The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is subsequently driven high after the clock oscillation stabilization time has passed, reset exception handling starts. Figure 18.4 shows an example of hardware standby mode timing.
Oscillator
RES
STBY
Oscillation stabilization time
Reset exception handling
Figure 18.4 Hardware Standby Mode Timing
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Section 18 Power-Down Modes
18.7
Watch Mode
The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and onchip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is exited by an interrupt (WOVI1, NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), RES pin input, or STBY pin input. When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, watch mode is not exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the onchip peripheral modules, watch mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the CPU. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode.
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Section 18 Power-Down Modes
18.8
Subsleep Mode
The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to IRQ7), the RES pin input, or the STBY pin input. When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts. In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the on-chip peripheral modules, subsleep mode is not exited if the interrupt enable register has been set to disable the reception of that interrupt, or the interrupt is masked by the CPU. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode.
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Section 18 Power-Down Modes
18.9
Subactive Mode
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at a low speed based on the subclock and sequentially executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to 0. Subactive mode is exited by the SLEEP instruction, RES pin input, or STBY pin input. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode. For details of direct transitions, see section 18.11, Direct Transitions. When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until the clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has passed, the CPU begins reset exception handling. If the STBY pin is driven low, the LSI enters hardware standby mode.
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Section 18 Power-Down Modes
18.10
Module Stop Mode
Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is released and the module operation resumes at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, D/A converter, A/D converter, and PWMX are retained. After the reset state is released, all modules are in module stop mode. While an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled.
18.11
Direct Transitions
The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a direct transition is made from high-speed mode to subactive mode, there is no interruption of program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and then executing the SLEEP instruction. After a transition, direct transition exception handling starts. The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 11, and the PSS bit in TSCR (WDT_1) set to 1. To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR (WDT_1) set to 1.
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Section 18 Power-Down Modes
18.12
Usage Notes
18.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 18.12.2 Current Consumption while Waiting for Oscillation to be Stabilized The current consumption while waiting for oscillation to be stabilized is higher than that while oscillation is stabilized.
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Section 19 List of Registers
Section 19 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * * 3. * * 4. * * Register Addresses (address order) Registers are listed from the lower allocation addresses. The MSB-side address is indicated for 16-bit addresses. Registers are classified by functional modules. The access size is indicated. Register Bits Bit configurations of the registers are described in the same order as the Register Addresses (address order) above. Reserved bits are indicated by in the bit name column. The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 16-bit registers are indicated from the bit on the MSB side. Register States in Each Operating Mode Register states are described in the same order as the Register Addresses (address order) above. The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Register Select Conditions Register states are described in the same order as the Register Addresses (address order) above. For details on the register select conditions, refer to section 3.2.2, System Control Register (SYSCR), 3.2.3, Serial Timer Control Register (STCR), 18.1.3, Module Stop Control Registers H, L (MSTPCRH, MSTPCRL), and the register descriptions for each module.
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Section 19 List of Registers
19.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Number of Access States 2
Register Name Keyboard comparator control register
Abbreviation KBCOMP
Number of Bits 8
Address H'FEE4
Module IrDA/ Extended A/D INT INT INT INT INT INT INT INT INT INT FLASH FLASH FLASH SYSTEM FLASH SYSTEM SYSTEM SYSTEM SYSTEM SCI_1 SCI_1 SCI_1
Data Bus Width 8
Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L Address break control register Break address register A Break address register B Break address register C Flash memory control register 1 Flash memory control register 2 Erase block register 1 System control register 2 Erase block register 2 Standby control register Low power control register Module stop control register H Module stop control register L Serial mode register_1 Bit rate register_1 Serial control register_1
ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 BRR_1 SCR_1
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 H'FF82 H'FF83 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF89 H'FF8A
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
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Section 19 List of Registers
Register Name Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 Timer interrupt enable register Timer control/status register Free running counter H Free running counter L Output control register AH Output control register BH Output control register AL Output control register BL Timer control register Timer output compare control register Input capture register AH Output control register ARH Input capture register AL Output control register ARL Input capture register BH Output control register AFH Input capture register BL Output control register AFL Input capture register CH Output compare register DMH Input capture register CL Output compare register DML Input capture register DH Input capture register DL Serial mode register_2
Abbreviation TDR_1 SSR_1 RDR_1 SCMR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF94 H'FF95 H'FF95 H'FF96 H'FF97 H'FF98 H'FF98 H'FF99 H'FF99 H'FF9A H'FF9A H'FF9B H'FF9B H'FF9C H'FF9C H'FF9D H'FF9D H'FF9E H'FF9F H'FFA0
Module SCI_1 SCI_1 SCI_1 SCI_1 FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT SCI_2
Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
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Section 19 List of Registers
Register Name PWM (D/A) control register PWM (D/A) data register AH PWM (D/A) data register AL Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 PWM (D/A) counter H PWM (D/A) data register BH PWM (D/A) counter L PWM (D/A) data register BL Timer control/status register_0 Timer counter_0 Timer counter_0 Port A output data register Port A input data register Port A data direction register Port 1 pull-up MOS control register Port 2 pull-up MOS control register Port 3 pull-up MOS control register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register
Abbreviation DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address H'FFA0 H'FFA0 H'FFA1 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA6 H'FFA6 H'FFA7 H'FFA7 H'FFA8 H'FFA8 (write) H'FFA9 (read) H'FFAA H'FFAB H'FFAB H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5
Module PWMX PWMX PWMX SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 PWMX PWMX PWMX PWMX WDT WDT_0 WDT_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT
Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 1.00 Jun.24, 2005 Page 410 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Name Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port B output data register Port B input data register Port 8 data direction register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register System control register Mode control register Bus control register Wait state control register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0
Abbreviation P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD (read) H'FFBD (write) H'FFBE (read) H'FFBE (write) H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE
Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT INT SYSTEM SYSTEM SYSTEM BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0
Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16
Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 1.00 Jun.24, 2005 Page 411 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Name Time constant register B_1 Timer counter_0 Timer counter_1 Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register_1 Timer counter_1
Abbreviation TCORB_1 TCNT_0 TCNT_1 SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address H'FFCF H'FFD0 H'FFD1 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEA (write)
Module TMR_1 TMR_0 TMR_1 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 A/D converter A/D converter A/D converter A/D converter A/D converter A/D converter A/D converter A/D converter A/D converter A/D converter WDT_1 WDT_1
Data Bus Width 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Number of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 1.00 Jun.24, 2005 Page 412 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Name Timer counter_1 Timer control register_Y Keyboard matrix interrupt register 6 Timer control/status register_Y Pull-up MOS control register Time constant register A_Y Keyboard matrix interrupt register A Time constant register B_Y Timer counter_Y Timer input select register D/A data register 0 D/A data register 1 D/A control register
Abbreviation TCNT_1 TCR_Y KMIMR TCSR_Y KMPCR TCORA_Y KMIMRA TCORB_Y TCNT_Y TISR DADR0 DADR1 DACR
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8
Address H'FFEB (read) H'FFF0 H'FFF1 H'FFF1 H'FFF2 H'FFF2 H'FFF3 H'FFF3 H'FFF4 H'FFF5 H'FFF8 H'FFF9 H'FFFA
Module WDT_1 TMR_Y INT TMR_Y PORT TMR_Y INT TMR_Y TMR_Y TMR_Y D/A converter D/A converter D/A converter
Data Bus Width 8 16 8 16 8 16 8 16 16 16 8 8 8
Numbe r of Access States 2 2 2 2 2 2 2 2 2 2 2 2 2
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Section 19 List of Registers
19.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. 16-bit registers are shown as 2 lines.
Register Abbreviation KBCOMP Bit 7 IrE Bit 6 IrCKS2 Bit 5 IrCKS1 Bit 4 IrCKS0 Bit 3 KBADE Bit 2 KBCH2 Bit 1 KBCH1 Bit 0 KBCH0 Module IrDA/ expande d A/D ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 BRR_1 ICRA7 ICRB7 ICRC7 IRQ7F IRQ7SCB IRQ3SCB CMF A23 A15 A7 FWE FLER -- KWUL1 EB7 SSBY DTON MSTP15 MSTP7 C/A Bit 7 ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA -- A22 A14 A6 SWE -- -- KWUL0 EB6 STS2 LSON MSTP14 MSTP6 CHR Bit 6 ICRA5 ICRB5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB -- A21 A13 A5 -- -- -- P6PUE EB5 STS1 NESEL MSTP13 MSTP5 PE Bit 5 ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA -- A20 A12 A4 -- -- -- -- EB4 STS0 EXCLE MSTP12 MSTP4 O/E Bit 4 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB -- A19 A11 A3 EV -- -- -- EB3 -- -- MSTP11 MSTP3 STOP Bit 3 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA -- A18 A10 A2 PV -- -- -- EB2 SCK2 -- MSTP10 MSTP2 MP Bit 2 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB -- A17 A9 A1 E ESU EB9 -- EB1 SCK1 -- MSTP9 MSTP1 CKS1 Bit 1 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA BIE A16 A8 -- P PSU EB8 -- EB0 SCK0 -- MSTP8 MSTP0 CKS0 Bit 0 SCI_1 SYSTEM FLASH SYSTEM FLASH INT
Rev. 1.00 Jun.24, 2005 Page 414 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL Bit 7 TIE Bit 7 TDRE Bit 7 -- ICIAE ICFA Bit 15 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 IEDGA ICRDMS Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 15 Bit 7 Bit 7 Bit 15 Bit 7 Bit 6 RIE Bit 6 RDRF Bit 6 -- ICIBE ICFB Bit 14 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 IEDGB OCRAMS Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 14 Bit 6 Bit 6 Bit 14 Bit 6 Bit 5 TE Bit 5 ORER Bit 5 -- ICICE ICFC Bit 13 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 IEDGC ICRS Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 13 Bit 5 Bit 5 Bit 13 Bit 5 Bit 4 RE Bit 4 FER Bit 4 -- ICIDE ICFD Bit 12 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 IEDGD OCRS Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 12 Bit 4 Bit 4 Bit 12 Bit 4 Bit 3 MPIE Bit 3 PER Bit 3 SDIR OCIAE OCFA Bit 11 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 BUFEA OEA Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 11 Bit 3 Bit 3 Bit 11 Bit 3 Bit 2 TEIE Bit 2 TEND Bit 2 SINV OCIBE OCFB Bit 10 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 BUFEB OEB Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 10 Bit 2 Bit 2 Bit 10 Bit 2 Bit 1 CKE1 Bit 1 MPB Bit 1 -- OVIE OVF Bit 9 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 CKS1 OLVLA Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 9 Bit 1 Bit 1 Bit 9 Bit 1 Bit 0 CKE0 Bit 0 MPBT Bit 0 SMIF -- CCLRA Bit 8 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 CKS0 OLVLB Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 8 Bit 0 Bit 0 Bit 8 Bit 0 FRT Module SCI_1
Rev. 1.00 Jun.24, 2005 Page 415 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR Bit 7 C/A TEST DA13 DA5 Bit 7 TIE Bit 7 TDRE Bit 7 -- UC7 DA13 UC8 DA5 OVF Bit 7 PA7ODR PA7PIN PA7DDR P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR P47DDR P37DR P47DR Bit 6 CHR PWME DA12 DA4 Bit 6 RIE Bit 6 RDRF Bit 6 -- UC6 DA12 UC9 DA4 WT/IT Bit 6 PA6ODR PA6PIN PA6DDR P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR P46DDR P36DR P46DR Bit 5 PE -- DA11 DA3 Bit 5 TE Bit 5 ORER Bit 5 -- UC5 DA11 UC10 DA3 TME Bit 5 PA5ODR PA5PIN PA5DDR P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR P45DDR P35DR P45DR Bit 4 O/E -- DA10 DA2 Bit 4 RE Bit 4 FER Bit 4 -- UC4 DA10 UC11 DA2 -- Bit 4 PA4ODR PA4PIN PA4DDR P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR P44DDR P34DR P44DR Bit 3 STOP OEB DA9 DA1 Bit 3 MPIE Bit 3 PER Bit 3 SDIR UC3 DA9 UC12 DA1 RST/NMI Bit 3 PA3ODR PA3PIN PA3DDR P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR P43DDR P33DR P43DR Bit 2 MP OEA DA8 DA0 Bit 2 TEIE Bit 2 TEND Bit 2 SINV UC2 DA8 UC13 DA0 CKS2 Bit 2 PA2ODR PA2PIN PA2DDR P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR P42DDR P32DR P42DR Bit 1 CKS1 OS DA7 CFS Bit 1 CKE1 Bit 1 MPB Bit 1 -- UC1 DA7 -- CFS CKS1 Bit 1 PA1ODR PA1PIN PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR P41DDR P31DR P41DR Bit 0 CKS0 CKS DA6 -- Bit 0 CKE0 Bit 0 MPBT Bit 0 SMIF UC0 DA6 REGS REGS CKS0 Bit 0 PA0ODR PA0PIN PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR P40DDR P30DR P40DR PORT WDT_0 PWMX SCI_2 Module SCI_2 PWMX
Rev. 1.00 Jun.24, 2005 Page 416 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 SMR_0 BRR_0 Bit 7 -- P67DDR -- P67DR PB7ODR PB7PIN -- P77PIN PB7DDR -- P97DDR P97DR IRQ7E IICS -- EXPE -- -- CMIEB CMIEB CMFB CMFB Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 C/A Bit 7 Bit 6 -- P66DDR -- P66DR PB6ODR PB6PIN P86DDR P76PIN PB6DDR P86DR P96DDR P96DR IRQ6E -- IOSE -- ICIS0 -- CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 CHR Bit 6 Bit 5 -- P65DDR -- P65DR PB5ODR PB5PIN P85DDR P75PIN PB5DDR P85DR P95DDR P95DR IRQ5E -- INTM1 -- BRSTRM ABW OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 PE Bit 5 Bit 4 -- P64DDR -- P64DR PB4ODR PB4PIN P84DDR P74PIN PB4DDR P84DR P94DDR P94DR IRQ4E IICE INTM0 -- BRSTS1 AST CCLR1 CCLR1 ADTE -- Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 O/E Bit 4 Bit 3 -- P63DDR -- P63DR PB3ODR PB3PIN P83DDR P73PIN PB3DDR P83DR P93DDR P93DR IRQ3E FLSHE XRST -- BRSTS0 WMS1 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 STOP Bit 3 Bit 2 P52DDR P62DDR P52DR P62DR PB2ODR PB2PIN P82DDR P72PIN PB2DDR P82DR P92DDR P92DR IRQ2E -- NMIEG -- -- WMS0 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 MP Bit 2 Bit 1 P51DDR P61DDR P51DR P61DR PB1ODR PB1PIN P81DDR P71PIN PB1DDR P81DR P91DDR P91DR IRQ1E ICKS1 HIE MDS1 IOS1 WC1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 CKS1 Bit 1 Bit 0 P50DDR P60DDR P50DR P60DR PB0ODR PB0PIN P80DDR P70PIN PB0DDR P80DR P90DDR P90DR IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 CKS0 Bit 0 SCI_0 TMR_0, TMR_1 BSC INT SYSTEM Module PORT
Rev. 1.00 Jun.24, 2005 Page 417 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCR_Y KMIMR TCSR_Y KMPCR TCORA_Y KMIMRA TCORB_Y TCNT_Y TISR DADR_0 DADR_1 DACR Bit 7 TIE Bit 7 TDRE Bit 7 -- AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit 7 CMIEB KMIMR7 CMFB KMIMR7 Bit 7 KMIMR15 Bit 7 Bit 7 -- Bit 7 Bit 7 DAOE1 Bit 6 RIE Bit 6 RDRF Bit 6 -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit 6 CMIEA KMIMR6 CMFA KMIMR6 Bit 6 KMIMR14 Bit 6 Bit 6 -- Bit 6 Bit 6 DAOE0 Bit 5 TE Bit 5 ORER Bit 5 -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- TME Bit 5 OVIE KMIMR5 OVF KMIMR5 Bit 5 KMIMR13 Bit 5 Bit 5 -- Bit 5 Bit 5 DAE Bit 4 RE Bit 4 FER Bit 4 -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- PSS Bit 4 CCLR1 KMIMR4 ICIE KMIMR4 Bit 4 KMIMR12 Bit 4 Bit 4 -- Bit 4 Bit 4 -- Bit 3 MPIE Bit 3 PER Bit 3 SDIR AD5 -- AD5 -- AD5 -- AD5 -- CKS -- RST/NMI Bit 3 CCLR0 KMIMR3 OS3 KMIMR3 Bit 3 KMIMR11 Bit 3 Bit 3 -- Bit 3 Bit 3 -- Bit 2 TEIE Bit 2 TEND Bit 2 SINV AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- CKS2 Bit 2 CKS2 KMIMR2 OS2 KMIMR2 Bit 2 KMIMR10 Bit 2 Bit 2 -- Bit 2 Bit 2 -- Bit 1 CKE1 Bit 1 MPB Bit 1 -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- CKS1 Bit 1 CKS1 KMIMR1 OS1 KMIMR1 Bit 1 KMIMR9 Bit 1 Bit 1 -- Bit 1 Bit 1 -- Bit 0 CKE0 Bit 0 MPBT Bit 0 SMIF AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- CKS0 Bit 0 CKS0 KMIMR0 OS0 KMIMR0 Bit 0 KMIMR8 Bit 0 Bit 0 IS Bit 0 Bit 0 -- D/A converter TMR_Y INT TMR_Y PORT TMR_Y INT TMR_Y WDT_1 A/D converter Module SCI_0
Rev. 1.00 Jun.24, 2005 Page 418 of 510 REJ09B0241-0100
Section 19 List of Registers
19.3
Register Abbreviation KBCOMP
Register States in Each Operating Mode
High-Speed/ MediumReset Initialized Speed -- Watch -- Sleep -- Sub-Active Sub-Sleep -- -- Module Stop -- Software Standby -- Hardware Standby Initialized Module IrDA/ A/D converter
ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Initialized -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Initialized -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Initialized -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized
-- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized -- Initialized -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
INT
INT
FLASH
SYSTEM FLASH SYSTEM
SCI_1
Rev. 1.00 Jun.24, 2005 Page 419 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation TIER TCSR FRCH FRCL OCRAH OCRBH OCRAL OCRBL TCR TOCR ICRAH OCRARH ICRAL OCRARL ICRBH OCRAFH ICRBL OCRAFL ICRCH OCRDMH ICRCL OCRDML ICRDH ICRDL SMR_2 DACR DADRAH DADRAL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ MediumSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sub-Active Sub-Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_2 PWMX Module FRT
Rev. 1.00 Jun.24, 2005 Page 420 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ MediumSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Watch Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sub-Active Sub-Sleep Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT WDT_0 PWMX Module SCI_2
Rev. 1.00 Jun.24, 2005 Page 421 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 SMR_0 BRR_0 Reset Initialized Initialized -- Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ MediumSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Watch -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sub-Active Sub-Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Module Stop -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Software Standby -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Hardware Standby Initialized Initialized -- Initialized -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0 TMR_0, TMR_1 BSC INT SYSTEM Module PORT
Rev. 1.00 Jun.24, 2005 Page 422 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Abbreviation SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCR_Y KMIMR TCSR_Y KMPCR TCORA_Y KMIMRA TCORB_Y TCNT_Y TISR DADR0 DADR1 DACR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
High-Speed/ MediumSpeed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Watch Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sub-Active Sub-Sleep Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized -- -- -- -- -- -- -- -- -- -- -- -- -- -- Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_Y INT TMR_Y PORT TMR_Y INT TMR_Y TMR_Y TMR_Y D/A converter WDT_1 A/D converter Module SCI_0
Rev. 1.00 Jun.24, 2005 Page 423 of 510 REJ09B0241-0100
Section 19 List of Registers
19.4
Lower Address H'FEE4
Register Select Conditions
Register Selected Conditions Register Name KBCOMP H8S/2144B Always selected H8S/2134B Always selected Module Name IrDA/ extended A/D INT
H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FF80 H'FF81 H'FF82 H'FF83
ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC FLMCR1 FLMCR2 EBR1 SYSCR2 EBR2
Always selected
Always selected
FLSHE = 1 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR
FLSHE = 1 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR FLSHE = 1 in STCR FLSHE = 0 in STCR
FLASH FLASH SYSTEM FLASH SYSTEM
H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF89
SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 BRR_1
MSTP6 = 0, IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR
MSTP6 = 0,IICE = 0 in STCR MSTP6 = 0, IICE = 0 in STCR
SCI_1
Rev. 1.00 Jun.24, 2005 Page 424 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Selected Conditions Lower Address H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 Register Name SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 TIER TCSR FRCH FRCL OCRAH OCRBH H'FF95 OCRAL OCRBL H'FF96 H'FF97 H'FF98 TCR TOCR ICRAH OCRARH H'FF99 ICRAL OCRARL H'FF9A ICRBH OCRAFH H'FF9B ICRBL OCRAFL H'FF9C ICRCH OCRDMH H'FF9D ICRCL OCRDML H'FF9E H'FF9F ICRDH ICRDL
ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR ICRS = 0 in TOCR ICRS = 1 in TOCR
H8S/2144B MSTP6 = 0
H8S/2134B MSTP6 = 0
Module Name SCI_1
MSTP6 = 0, IICE = 0 in STCR MSTP13 = 0
MSTP6 = 0, IICE = 0 in STCR MSTP13 = 0 FRT
MSTP13 = 0
OCRS = 0 in TOCR OCRS = 1 in TOCR OCRS = 0 in TOCR OCRS = 1 in TOCR
MSTP13 = 0
OCRS = 0 in TOCR OCRS = 1 in TOCR OCRS = 0 in TOCR OCRS = 1 in TOCR
Rev. 1.00 Jun.24, 2005 Page 425 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Selected Conditions Lower Address H'FFA0 Register Name SMR_2 DADRAH DACR H'FFA1 BRR_2 DADRAL H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADRBH DACNTH H'FFA7 DADRBL DACNTL H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD H'FFAE TCSR_0 TCNT_0 (write) TCNT_0 (read) PAODR PAPIN (read) PADDR (write) P1PCR P2PCR P3PCR Always selected Always selected PORT MSTP5 = 0, IICE = 0 in STCR
MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/DADRB REGS = 1 in DACNT/DADRB REGS = 0 in DACNT/DADRB REGS = 1 in DACNT/DADRB
H8S/2144B MSTP5 = 0, IICE = 0 in STCR
MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/DADRB REGS = 1 in DACNT/DADRB
H8S/2134B MSTP5 = 0, IICE = 0 in STCR
MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/DADRB REGS = 1 in DACNT/DADRB
Module Name SCI_2 PWMX
MSTP5 = 0, IICE = 0 in STCR
MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/DADRB
MSTP5 = 0, IICE = 0 in STCR
MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/DADRB
SCI_2 PWMX SCI_2
MSTP5 = 0
MSTP5 = 0
MSTP5 = 0, IICE = 0 in STCR
MSTP11 = 0, IICE = 1 in STCR REGS = 0 in DACNT/DADRB REGS = 1 in DACNT/DADRB REGS = 0 in DACNT/DADRB REGS = 1 in DACNT/DADRB
SCI_2 PWMX
Always selected
Always selected
WDT_0
Rev. 1.00 Jun.24, 2005 Page 426 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Selected Conditions Lower Address H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB Register Name P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR (write) PBPIN (read) P7PIN (read) PBDDR (write) P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 MSTP12 = 0 MSTP12 = 0 TMR_0, TMR_1 Always selected Always selected BSC Always selected Always selected Always selected Always selected INT SYSTEM H8S/2144B Always selected H8S/2134B Always selected Module Name PORT
Rev. 1.00 Jun.24, 2005 Page 427 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Selected Conditions Lower Address H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFF0 Register Name TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 (write) TCNT_1 (read) TCR_Y MSPT8 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR TMR_Y Always selected Always selected WDT_1 MSTP7 = 0, IICE = 0 in STCR MSTP9 = 0 MSTP7 = 0, IICE = 0 in STCR MSTP9 = 0 A/D MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0 MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0, IICE = 0 in STCR MSTP7 = 0 SCI_0 SCI_0 SCI_0 H8S/2144B MSTP12 = 0 H8S/2134B MSTP12 = 0 Module Name TMR_0, TMR_1
Rev. 1.00 Jun.24, 2005 Page 428 of 510 REJ09B0241-0100
Section 19 List of Registers
Register Selected Conditions Lower Address H'FFF1 Register Name KMIMR TCSR_Y H'FFF2 KMPCR TCORA_Y H'FFF3 KMIMRA TCORB_Y H'FFF4 H'FFF5 H'FFF8 H'FFF9 H'FFFA TCNT_Y TISR DADR0 DADR1 DACR H8S/2144B MSPT2 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSTP10 = 0 H8S/2134B MSPT2 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSTP2 = 0, HIE = 1 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSPT8 = 0, HIE = 0 in SYSCR MSTP10 = 0 D/A Module Name INT TMR_Y PORT TMR_Y INT TMR_Y
Rev. 1.00 Jun.24, 2005 Page 429 of 510 REJ09B0241-0100
Section 19 List of Registers
Rev. 1.00 Jun.24, 2005 Page 430 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Section 20 Electrical Characteristics
20.1
20.1.1
Electrical Characteristics of H8S/2144B
Absolute Maximum Ratings
Table 20.1 lists the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings
Item Power supply voltage I/O buffer power supply voltage (port A) Power supply (VCL input)* Input voltage (other than ports 6, 7, and A) Input voltage (CIN input not selected for port 6) Input voltage (CIN input not selected for port A) Input voltage (CIN input selected for port 6) Input voltage (CIN input selected for port A) Input voltage (port 7) Reference supply voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC VCCB VCL Vin Vin Vin Vin Vin Vin AVref AVCC VAN Topr Value -0.3 to +7.3 -0.3 to +7.0 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCCB +0.3 -0.3 V to lower of voltages VCC + 0.3 and AVCC + 0.3 -0.3 V to lower of voltages VCCB + 0.3 and AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 General specifications: -20 to +75 Wide temperature range specifications: -40 to +85 Operating temperature (flash memory programming/erasing) Topr General specifications: -20 to +75 Wide temperature range specifications: -40 to +85 Storage temperature Caution: Tstg -55 to +125 C Operating this LSI in excess of the absolute maximum ratings may result in permanent damage. Do not apply a voltage exceeding 7.0 V to input pins for the 5-V/4-V operation products. Power supply pin for the internal power supply. Do not apply a power to the VCL pin for the 5-V/4-V operation products. Connect a capacitor for regulating the internal power voltage between the VCL and GND pins.
Rev. 1.00 Jun.24, 2005 Page 431 of 510 REJ09B0241-0100
Unit V V V V V V V V V V V V C
C
Note:
*
Section 20 Electrical Characteristics
20.1.2
DC Characteristics
Table 20.2 lists the DC characteristics. Permissible output current values and bus driving characteristics are shown in tables 20.3 and 20.4, respectively. Table 20.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, AVCC*1 = 5.0 V 10%, AVref*1 = 4.5 V to AVCC, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Schmitt P67 to P60 (1) trigger input (KWUL = voltage 00)*2*4, KIN15 to 56 KIN8* * , IRQ2 to IRQ0*3, IRQ5 to IRQ3 Schmitt P67 to P60 trigger input (KWUL = 01) voltage (level 4 switching)* P67 to P60 (KWUL = 10) Symbol VT VT
- +
Min. 1.0 --
Typ. Max. -- -- -- -- VCC x 0.7 VCCB x 0.7 --
Unit V
Test Conditions
VT - VT
+
-
0.4
VT- VT VT VT VT VT
+
VCC x 0.3 --
-
-- -- -- -- -- -- -- -- -- -- -- --
-- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 VCCB + 0.3 AVCC + 0.3 VCC + 0.3
V
VT - VT
- +
+
VCC x 0.05 VCC x 0.4 --
VT - VT P67 to P60 (KWUL = 11)
- +
+
-
VCC x 0.03 VCC x 0.45 -- 0.05 VCC x 0.7 VCC x 0.7
+ - VT - VT
Input high voltage
RES, STBY, (2) NMI, MD1, MD0 EXTAL PA7 to PA0* Port 7 Input pins except (1) and (2) above
5
VIH
V
VCCB x 0.7 2.0 2.0
Rev. 1.00 Jun.24, 2005 Page 432 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Item Input low voltage RES, STBY, MD1, MD0 PA7 to PA0 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage (3)
Symbol VIL
Min. -0.3 -0.3 -0.3
Typ. -- -- --
Max. 0.5 1.0 0.8
Unit V
Test Conditions
VOH
VCC - 0.5 -- VCCB - 0.5 3.5 -- -- -- -- -- -- --
-- -- 0.4 1.0 0.4
V V V V V
IOH = -200 A IOL = -1 mA IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA
Output low voltage
All output pins (except RESO) Ports 1 to 3 RESO
VOL
Notes: 1. Do not leave the AVcc, AVref, and AVss pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVcc and AVref pins to the power supply (VCC), or some other method. Be sure that AVref AVCC. 2. Characteristics for P67 to P60 also indicate those for multiplexed signals of on-chip peripheral modules. 3. Characteristic for IRQ2 also indicate that for the multiplexed ADTRG signal. 4. The upper limit of the applicable voltage for port 6 is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is the applicable voltage. 5. The upper limit of the applicable voltage for port A is VCCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is the applicable voltage. 6. The port A characteristics depend on VCCB, and the characteristics for other pins depend on VCC.
Rev. 1.00 Jun.24, 2005 Page 433 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Table 20.2 DC Characteristics (2) Conditions: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, AVCC*1 = 5.0 V 10%, AVref*1 = 4.5 V to AVCC, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Tri-state leakage current (off state) Input pull-up MOS current Ports 1 to 6, 8, 9, A*4, ITSI B Symbol Min. Iin -- -- -- -- Typ. -- -- -- -- Max. 10.0 1.0 1.0 1.0 A Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V, Vin = 0.5 to VCCB - 0.5 V Vin = 0 V
Ports 1 to 3 Ports A* , B, 6 (P6PUE = 1) Port 6 (P6PUE = 1)
4
-IP
30 60 15 -- -- --
-- -- -- -- -- -- 55 36 1.0 -- 1.2 0.01
300 600 200 80 50 15 70 55 5.0 20.0 2.0 5.0
A
Input RES capacitance NMI
(4) Cin
pF
Input pins except (4) above Current consumption*2 Normal operation Sleep mode Standby mode*
3
Vin = 0 V, f = 1 MHz, Ta = 25C
ICC
-- -- -- --
mA mA A
f = 20 MHz f = 20 MHz Ta 50C 50C < Ta
Analog power supply current
During A/D, D/A conversion
AlCC
-- --
mA
Idle
A
AVCC = 2.0 V to 5.5 V
Rev. 1.00 Jun.24, 2005 Page 434 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Item Reference power supply current
Symbol
Min. -- -- --
Typ. 0.5 2.0 0.01 -- -- --
Max. 1.0 5.0 5.0 5.5 5.5 --
Unit mA
Test Conditions
During A/D conversion Alref During A/D, D/A conversion Idle
A V
AVref = 2.0 V to AVCC Operating Idle/not used
Analog power supply voltage*1
AVCC
4.5 2.0
RAM standby voltage
VRAM
2.0
V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVcc and AVref pins to the power supply (VCC), or some other method. Be sure that AVref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VCCB - 0.2 V, and VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs disabled. 3. The values are for VRAM VCC < 4.5 V, VIH min. = VCC- 0.2 V, VCCB - 0.2 V, and VIL max. = 0.2 V. 4. The port A characteristics depend on VCCB, and the characteristics for other pins depend on VCC.
Rev. 1.00 Jun.24, 2005 Page 435 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Table 20.2 DC Characteristics (3) Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, AVref*1 = 4.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Schmitt P67 to P60 (1) trigger input (KWUL = voltage 00)*2*4, KIN15 to 56 KIN8* * , IRQ2 to IRQ0*3, IRQ5 to IRQ3 Symbol VT VT
- +
Min. 1.0 -- 0.4 0.8 --
Typ. Max. -- -- -- -- -- -- VCC x 0.7 VCCB x 0.7 -- -- VCC x 0.7 VCCB x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 VCCB + 0.3 AVCC + 0.3 VCC + 0.3
Test Unit Conditions V VCC = 4.5 V to 5.5 V VCCB = 4.5 V to 5.5 V VCC = 4.0 V to 4.5 V VCCB = 4.0 V to 4.5 V
VT+ - VT- VT VT
- +
V
+ - VT - VT
0.3 VCC x 0.3 -- VCC x 0.05 VCC x 0.4 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Schmitt P67 to P60 trigger input (KWUL = 01) voltage (level 4 switching)* P67 to P60 (KWUL = 10)
VT VT VT VT VT VT
-
V
+
VCC = 4.0 V to 5.5 V
+ - VT - VT -
+
VT - VT P67 to P60 (KWUL = 11)
- +
+
-
VCC x 0.03 VCC x 0.45 --
VT - VT Input high voltage RES, STBY, (2) NMI, MD1, MD0 EXTAL PA7 to PA0* Port 7 Input pins except (1) and (2) above
5
+
-
0.05 VCC - 0.7 VCC x 0.7 VCCB x 0.7 2.0 2.0
VIH
V
Rev. 1.00 Jun.24, 2005 Page 436 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Item Input low voltage RES, STBY, MD1, MD0 (3)
Symbol VIL
Min. -0.3 -0.3 -0.3 -0.3
Typ. -- -- -- --
Max. 0.5 1.0 0.8 0.8
Test Unit Conditions V VCCB = 4.5 V to 5.5 V VCCB = 4.0 V to 4.5 V
PA7 to PA0 NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage VOH
VCC - 0.5 -- VCCB - 0.5 3.5 --
-- --
V V
IOH = -200 A IOH = -1 mA, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V IOH = -1 mA, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA
3.0
--
--
V
Output low voltage
All output pins (except RESO) Ports 1 to 3 RESO
VOL
-- -- --
-- -- --
0.4 1.0 0.4
V V V
Notes: 1. Do not leave the AVcc, AVref, and AVss pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVcc and AVref pins to the power supply (VCC), or some other method. Be sure that AVref AVCC. 2. Characteristics for P67 to P60 also indicate those for multiplexed signals of on-chip peripheral modules. 3. Characteristic for IRQ2 also indicate that for the multiplexed ADTRG signal. 4. The upper limit of the applicable voltage for port 6 is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is the applicable voltage. 5. The upper limit of the applicable voltage for port A is VCCB + 0.3 V when CIN input is not selected, and the lower of VCCB + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is the applicable voltage. 6. The port A characteristics depend on VCCB, and the characteristics for other pins depend on VCC.
Rev. 1.00 Jun.24, 2005 Page 437 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Table 20.2 DC Characteristics (4) Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, AVref*1 = 4.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Tri-state leakage current (off state) Input pull-up MOS current Ports 1 to 6, 8, 9, A*4, B ITSI Symbol Iin Min. -- -- -- -- Typ. -- -- -- -- Max. 10.0 1.0 1.0 1.0 A Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V, Vin = 0.5 to VCCB - 0.5 V Vin = 0 V, VCC = 4.5 V to 5.5 V VCCB = 4.5 V to 5.5 V Vin = 0 V, VCC = 4.0 V to 4.5 V VCCB = 4.0 V to 4.5 V Vin = 0 V, f = 1 MHz, Ta = 25C
Ports 1 to 3 Ports A* , B, 6 (P6PUE = 1) Port 6 (P6PUE = 1) Ports 1 to 3 Ports A* , B, 6 (P6PUE = 1) Port 6 (P6PUE = 1)
4 4
-IP
30 60 15 20 40 10
-- -- -- -- --
300 600 200 200 500 150
A
A
Input RES capacitance NMI
(4)
Cin
-- -- --
-- -- -- 45 30 1.0 --
80 50 15 58 46 5.0 20.0
pF
Input pins except (4) above Current consumption*2 Normal operation Sleep mode Standby mode*
3
ICC
-- -- -- --
mA mA A
f = 16 MHz f = 16 MHz Ta 50C 50C < Ta
Rev. 1.00 Jun.24, 2005 Page 438 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Item Analog power supply current Reference power supply current During A/D, D/A conversion Idle
Symbol AlCC
Min. -- -- -- -- --
Typ. 1.2 0.01 0.5 2.0 0.01 -- -- --
Max. 2.0 5.0 1.0 5.0 5.0 5.5 5.5 --
Unit mA A mA
Test Conditions
AVCC = 2.0 V to 5.5 V
During A/D conversion Alref During A/D, D/A conversion Idle
A V
AVref = 2.0 V to AVCC Operating Idle/not used
Analog power supply voltage*1
AVCC VRAM
4.0 2.0
RAM standby voltage
2.0
V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVcc and AVref pins to the power supply (VCC), or some other method. Be sure that AVref AVCC. 2. Current consumption values are for VIH min. = VCC - 0.2 V, VCCB - 0.2 V, and VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs disabled. 3. The values are for VRAM VCC < 4.0 V, VIH min. = VCC- 0.2 V, VCCB - 0.2 V, and VIL max. = 0.2 V. 4. The port A characteristics depend on VCCB, and the characteristics for other pins depend on VCC.
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Section 20 Electrical Characteristics
Table 20.3 Permissible Output Currents Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Permissible output low current (per pin) PA7 to PA4 (bus driving function selected) Ports 1 to 3 RESO Other output pins Permissible output low current (total) Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min. -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- Max. 20 10 3 2 80 120 2 40 mA mA mA Unit mA
Permissible output high current (per pin) Permissible output high current (total)
Notes: 1. To ensure reliability, do not exceed the output current values in table 20.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 20.1 and 20.2.
This LSI
2 k Port
Darlington pair
Figure 20.1 Darlington Pair Driving Circuit (Example)
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Section 20 Electrical Characteristics
This LSI
600 Ports 1 to 3
LED
Figure 20.2 LED Driving Circuit (Example) Table 20.4 Bus Driving Characteristics Conditions: VCCB = 4.0 V to 5.5 V, VSS = 0 V
Applicable Pins: PA7 to PA4 (bus driving function selected)
Item Output low voltage Symbol VOL Min. -- -- -- Typ. -- -- -- Max. 0.8 0.5 0.4 Unit V Test Conditions IOL = 16 mA, VCCB = 4.5 V to 5.5 V IOL = 8 mA IOL = 3 mA
20.1.3
AC Characteristics
Figure 20.3 shows the test conditions for the AC characteristics.
VCC RL LSI output pin C = 30 pF: All output ports RL = 2.4 k RH = 12 k I/O timings are measured: * at 0.8 V for the low level * at 2.0 V for the high level
C
RH
Figure 20.3 Output Load Circuit
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Section 20 Electrical Characteristics
Clock Timing: Table 20.5 shows the clock timing. The clock timing specified here covers clock () output and oscillation stabilization times of the clock pulse generator (crystal) and external clock input (the EXTAL pin). For details on external clock input (the EXTAL pin and EXCL pin) timing, see section 17, Clock Pulse Generator. Table 20.5 Clock Timing Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rising time Clock falling time Symbol Min. tcyc tCH tCL tCr tCf 62.5 20 20 -- -- 10 8 500 Max. 500 -- -- 10 10 -- -- -- Condition A 20 MHz Min. 50 17 17 -- -- 10 8 500 Max. 500 -- -- 8 8 -- -- -- Unit ns ns ns ns ns ms ms s Figure 20.5 Figure 20.6 Reference Figure 20.4 Figure 20.4
Oscillation stabilization time at reset tOSC1 (crystal) Oscillation stabilization time at leaving software standby (crystal) External clock output stabilization delay time tOSC2 tDEXT
tcyc
tCH
tCf
tCL
tCr
Figure 20.4 System Clock Timing
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Section 20 Electrical Characteristics
EXTAL
tDEXT
tDEXT
VCC
STBY tOSC1 RES tOSC1
Figure 20.5 Oscillation Stabilization Timing
NMI
IRQi (i = 0, 1, 2, 6, 7)
tOSC2
Figure 20.6 Oscillation Stabilization Timing (Leaving Software Standby Mode)
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Section 20 Electrical Characteristics
Control Signal Timing: Table 20.6 shows the control signal timing. The only external interrupts that can be received during this LSI operating on the subclock ( = 32.768 kHz) are NMI, IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 20.6 Control Signal Timing Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 32.768 kHz or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 32.768 kHz or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B Condition A 16 MHz Item RES setup time RES pulse width NMI setup time (NMI) NMI hold time (NMI) NMI pulse width (leaving software standby mode) IRQ setup time (IRQ7 to IRQ0) IRQ hold time(IRQ7 to IRQ0) IRQ pulse width (IRQ7, IRQ6, IRQ2 to IRQ0) (leaving software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- 20 MHz Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- Unit ns tcyc ns ns ns ns ns ns Figure 20.8 Test Conditions Figure 20.7
tRESS RES
tRESS
tRESW
Figure 20.7 Reset Input Timing
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Section 20 Electrical Characteristics
tNMIS
NMI tNMIW
tNMIH
IRQi (i = 7 to 0) tIRQS
tIRQW tIRQH
IRQi Edge input (i = 7 to 0)
tIRQS
IRQi Level input (i = 7 to 0)
Figure 20.8 Interrupt Input Timing Bus Timing: Table 20.7 shows the bus timing. Operation in external extended mode is not guaranteed when this LSI is operating on the subclock ( = 32.768 kHz).
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Section 20 Electrical Characteristics
Table 20.7 Bus Timing (1) (Normal Mode) Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time
Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5
Condition A 20 MHz Min. -- 0.5 x tcyc - 15 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- -- -- Max. 20 -- -- 20 30 30 30 -- -- 1.0 x tcyc - 30 1.5 x tcyc - 25 2.0 x tcyc - 30 2.5 x tcyc - 25 3.0 x tcyc - 30 30 30 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figures 20.9 to 20.13
Symbol Min. tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- -- 20 0 -- -- -- -- -- -- --
Max. 30 -- -- 30 45 45 45 -- -- 1.0 x tcyc - 40 1.5 x tcyc - 35 2.0 x tcyc - 40 2.5 x tcyc - 35 3.0 x tcyc - 40 45 45
HWR, LWR delay time 1 tWRD1 HWR, LWR delay time 2 tWRD2
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Section 20 Electrical Characteristics
Condition B 16 MHz Item Symbol Min. 1.0 x tcyc - 30 1.5 x tcyc - 30 -- 0 15 45 5 Max. -- -- 45 -- -- -- --
Condition A 20 MHz Min. 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0 10 30 5 Max. -- -- 30 -- -- -- -- Test Unit Conditions ns ns ns ns ns ns ns Figures 20.9 to 20.13
HWR, LWR pulse width 1 tWSW1 HWR, LWR pulse width 2 tWSW2
Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time
tWDD tWDS tWDH tWTS tWTH
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Section 20 Electrical Characteristics
Table 20.7 Bus Timing (2) (Advanced Mode) Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time
Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5
Condition A 20 MHz Min. -- 0.5 x tcyc - 25 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- -- -- Max. 30 -- -- 30 30 30 30 -- -- 1.0 x tcyc - 40 2.5 x tcyc - 25 3.0 x tcyc - 40 2.5 x tcyc - 25 3.0 x tcyc - 40 30 30 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figures 20.9 to 20.13
Symbol Min. tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 -- 0.5 x tcyc - 35 0.5 x tcyc - 15 -- -- -- -- 20 0 -- -- -- -- -- -- --
Max. 45 -- -- 45 45 45 45 -- -- 1.0 x tcyc - 55 2.5 x tcyc - 35 3.0 x tcyc - 55 2.5 x tcyc - 35 3.0 x tcyc - 55 45 45
HWR, LWR delay time 1 tWRD1 HWR, LWR delay time 2 tWRD2
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Section 20 Electrical Characteristics
Condition B 16 MHz Item Symbol Min. 1.0 x tcyc - 30 1.5 x tcyc - 30 -- 0 15 45 5 Max. -- -- 45 -- -- -- --
Condition A 20 MHz Min. 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0 10 30 5 Max. -- -- 30 -- -- -- -- Test Unit Conditions ns ns ns ns ns ns ns Figures 20.9 to 20.13
HWR, LWR pulse width 1 tWSW1 HWR, LWR pulse width 2 tWSW2
Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time
tWDD tWDS tWDH tWTS tWTH
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Section 20 Electrical Characteristics
T1
T2
tAD A23 to A0, IOS* tCSD AS* tAS tAH tASD tASD
tRSD1 RD (read) tAS
tACC2
tRSD2
tACC3 D15 to D0 (read)
tRDS
tRDH
tWRD2 HWR, LWR (write) tAS tWDD D15 to D0 (write) tWSW1
tWRD2 tAH tWDH
Note:* AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.9 Basic Bus Timing (Two-State Access)
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Section 20 Electrical Characteristics
T1
T2
T3
tAD
A23 to A0, IOS*
tCSD
tAS
tASD
tASD
tAH
AS*
tRSD1 RD (read)
tAS
tACC4
tRSD2
tACC5 D15 to D0 (read)
tRDS
tRDH
tWRD1 HWR, LWR (write)
tWDD tWDS
tWRD2
tAH
tWSW2
tWDH
D15 to D0 (write)
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.10 Basic Bus Timing (Three-State Access)
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Section 20 Electrical Characteristics
T1
T2
TW
T3
A23 to A0, IOS*
AS*
RD (read) D15 to D0 (read) HWR, LWR (write)
D15 to D0 (write)
tWTS tWTH
WAIT tWTS tWTH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.11 Basic Bus Timing (Three-State Access with One Wait Cycle)
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Section 20 Electrical Characteristics
T1
T2 or T3
T1
T2
tAD
A23 to A0, IOS*
tAS
tASD tASD
tAH
AS*
tRSD2
RD (read)
tACC3 D15 to D0 (read)
tRDS
tRDH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.12 Burst ROM Access Timing (Two-State Access)
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Section 20 Electrical Characteristics
T1
T2 or T3
T1
tAD
A23 to A0, IOS*
AS*
tRSD2
RD (read)
tACC1 D15 to D0 (read)
tRDS
tRDH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.13 Burst ROM Access Timing (One-State Access)
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Section 20 Electrical Characteristics
Timing of On-Chip Peripheral Modules: Tables 20.8 shows the on-chip peripheral module timing. The only on-chip peripheral modules that can operate during this LSI operating on the subclock ( = 32.768 kHz) are the I/O ports, external interrupts (NMI, IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7), watchdog timer, and the 8-bit timer (channels 0 and 1). Table 20.8 Timing of On-Chip Peripheral Modules Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, VSS = 0 V, = 32.768 kHz* or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, = 32.768 kHz* or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = - 40 to +85C (Wide temperature range specifications) Note: * For modules that can operate during this LSI operating on the subclock
Condition B 16 MHz Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Both edges Condition A 20 MHz Test Conditions Figure 20.14
Symbol Min. Max. Min. Max. Unit tPWD tPRS tPRH tFTOD tFTIS tFTCS -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 -- 50 -- -- 50 -- -- -- -- 50 -- -- -- -- 50 -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 -- 50 -- -- 50 -- -- -- -- 50 -- -- -- -- 50 ns tcyc ns tcyc ns ns
Figure 20.15 Figure 20.16
Single edge tFTCWH tFTCWL tTMOD tTMRS tTMCS
Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Both edges
Figure 20.17 Figure 20.19 Figure 20.18
Single edge tTMCWH tTMCWL tPWOD
PWMX
Pulse output delay time
Figure 20.20
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Section 20 Electrical Characteristics
Condition B 16 MHz Item SCI Input clock cycle
Condition A 20 MHz Test Conditions Figure 20.21
Symbol Min. Max. Min. Max. Unit Asynchronous tScyc Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS tRESD tRESOW 4 6 0.4 -- -- -- 50 50 30 -- 132 -- -- 0.6 1.5 1.5 50 -- -- -- 120 -- 4 6 0.4 -- -- -- 50 50 30 -- 132 -- -- 0.6 1.5 1.5 50 -- -- -- 100 -- ns ns tcyc ns tScyc tcyc tcyc
Input clock pulse width Input clock rising time Input clock falling time SCI Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter WDT RESO output delay time RESO output pulse width Note: *
Figure 20.22
Figure 20.23 Figure 20.24
Only on-chip peripheral modules that can be used in subclock operation
T1
T2
tPRS tPRH
Ports 1 to 9, A, and B (read)
tPWD
Ports 1 to 6, 8, 9, A, and B (write)
Figure 20.14 I/O Port Input/Output Timing
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Section 20 Electrical Characteristics
tFTOD FTOA, FTOB tFTIS
FTIA, FTIB, FTIC, FTID
Figure 20.15 FRT Input/Output Timing
tFTCS FTCI tFTCWL tFTCWH
Figure 20.16 FRT Clock Input Timing
tTMOD
TMO0, TMO1
Figure 20.17 8-Bit Timer Output Timing
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Section 20 Electrical Characteristics
tTMCS
tTMCS
TMCI0, TMCI1, TMIY
tTMCWL tTMCWH
Figure 20.18 8-Bit Timer Clock Input Timing
tTMRS
TMRI0, TMRI1, TMIY
Figure 20.19 8-Bit Timer Reset Input Timing
tPWOD
PWX1, PWX0
Figure 20.20 PWMX Output Timing
tSCKW tSCKr tSCKf
SCK0 to SCK2
tScyc
Figure 20.21 SCK Clock Input Timing
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Section 20 Electrical Characteristics
SCK0 to SCK2
tTXD
TxD0 to TxD2 (transmit data)
tRXS
tRXH
RxD0 to RxD2 (receive data)
Figure 20.22 SCI Input/Output Timing (Synchronous Mode)
tTRGS ADTRG
Figure 20.23 A/D Converter External Trigger Input Timing
tRESD RESO tRESOW tRESD
Figure 20.24 WDT Output Timing (RESO)
Testing voltage: 0.4Vcc 50 pF
Figure 20.25 Tester Measurement Condition
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Section 20 Electrical Characteristics
20.1.4
A/D Conversion Characteristics
Tables 20.9 and 20.10 list the A/D conversion characteristics. Table 20.9 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Resolution Conversion time*3 Analog input capacitance -- -- -- -- -- Min. Typ. 10 8.4 20 10* 5* Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy -- -- -- -- -- -- -- -- -- --
2 1
Condition A 20 MHz
Max.
Min.
Typ. 10
Max.
Unit bits
-- -- --
-- -- --
6.7 20 10* 5*
2 1
s pF k
Permissible signal-source impedance --
3.0 3.5 3.5 0.5 4.0
-- -- -- -- --
-- -- -- -- --
3.0 3.5 3.5 0.5 4.0
LSB LSB LSB LSB LSB
Notes: 1. When conversion time 11.17 s ( 12 MHz with CKS = 1 or CKS = 0) 2. When conversion time < 11.17 s ( > 12 MHz with CKS = 1) 3. When this LSI operates on the maximum operating frequency in single-chip mode
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Section 20 Electrical Characteristics
Table 20.10 A/D Conversion Characteristics (CIN15 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Resolution Conversion time*
3
Condition A 20 MHz
Min.
Typ. 10
Max.
Min.
Typ. 10
Max.
Unit bits
-- --
-- -- --
8.4 20 10* 5*
2 1
-- -- --
-- -- --
6.7 20 10* 5*
2 1
s pF k
Analog input capacitance
Permissible signal-source impedance --
Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
-- -- -- -- --
-- -- -- -- --
5.0 5.5 5.5 0.5 6.0
-- -- -- -- --
-- -- -- -- --
5.0 5.5 5.5 0.5 6.0
LSB LSB LSB LSB LSB
Notes: 1. When conversion time 11.17 s ( 12 MHz with CKS = 1 or CKS = 0) 2. When conversion time < 11.17 s ( > 12 MHz with CKS = 1) 3. When this LSI operates on the maximum operating frequency in single-chip mode
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Section 20 Electrical Characteristics
20.1.5
D/A Conversion Characteristics
Table 20.11 lists the D/A conversion characteristics. Table 20.11 D/A Conversion Characteristics Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Resolution Conversion time Absolute accuracy With 20 pF load capacitance -- With 2 M load resistance With 4 M load resistance -- -- Condition A 20 MHz
Min. Typ. Max. Min. Typ. Max. Unit 8 -- 10 -- 8 -- 10 bits s
1.0 1.5 -- -- 1.0 --
1.0 1.5 LSB -- 1.0
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Section 20 Electrical Characteristics
20.1.6
Flash Memory Characteristics
Table 20.12 shows the flash memory characteristics. Table 20.12 Flash Memory Characteristics (Programming/Erasure) Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (General specifications), Ta = - 40 to +85C (Wide temperature range specifications)
Item Programming time* * *
1 2 4
Symbol Min. tP --
Typ. 10
Max. 200
Unit ms/ 128 bytes ms/ block times s s s s s s s s s s s times
Test Condition
Erasure time*1*3*6 Reprogramming count Programming Wait time after setting SWE bit*1 Wait time after setting PSU bit*1 Wait time after setting P bit*1*4
tE NWEC x y z1 z2 z3
-- -- 1 50 28 198 8 5 5 4 2 2 100 --
100 -- -- -- 30 200 10 -- -- -- -- -- -- --
1200 100 -- -- 32 202 12 -- -- -- -- -- -- 1000
1n6 7n 1000 Additional write
Wait time after clearing P bit *1 Wait time after 1 clearing PSU bit * Wait time after setting PV bit *1 Wait time after dummy write*1 Wait time after 1 clearing PV bit * Wait time after clearing SWE bit *1 Maximum programming count*1*4*5
N
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Section 20 Electrical Characteristics
Item Erasure Wait time after setting SWE bit*1 Wait time after 1 setting ESU bit* Wait time after 16 setting E bit* * Wait time after 1 clearing E bit* Wait time after 1 clearing ESU bit* Wait time after 1 setting EV bit* Wait time after dummy-writing 1 H'FF* Wait time after 1 clearing EV bit* Wait time after 1 clearing SWE bit* Maximum erasure 167 count* * *
Symbol Min. x y z 1 100 10 10 10 20 2
Typ. -- -- -- -- -- -- --
Max. -- -- 100 -- -- -- --
Unit s s ms s s s s
Test Conditions
N
4 100 --
-- -- --
-- -- 120
s s times
Notes: 1. Set the times according to the programming/erasing algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the programming-verifying time.) 3. Block erasing time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erasing-verifying time.) 4. Maximum programming time (tP (max.)) tP (max.) = (wait time after setting P bit (z1) + (z3)) x 6 + wait time after setting P bit (z2) x ((N) - 6) 5. The maximum programming court (N) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (tP (max.)). The wait time after setting the P bit (z1, z2, and z3) should be alternated according to the programming count (n) as follows: 1n6 z1 = 30s, z3 = 10s 7 n 1000 z2 = 200s 6. Maximum erasure time (tE (max.)) tE (max.) = Wait time after setting E bit (z) x maximum erasure count (N) 7. The maximum erasure count (N) should be set according to the actual set value of z to allow erasing within the maximum erasure time (tE (max.)).
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Section 20 Electrical Characteristics
20.1.7
Usage Note
* LSI with Internal Step-Down Circuit This LSI includes an internal step-down circuit which automatically step down the internal power voltage to an appropriate level. A capacitor or capacitors for regulating the internal power voltage (one 0.47-F capacitor or two 0.47-F capacitors in parallel) must be placed between the internal step-down and VSS pins. For connection of the capacitor, see figure 20.26.
External capacitor for regulating internal power voltage
VCL
0.47 F x 1 or 0.47 F x 2 in parallel
LSI with internal step-down circuit
VSS
Do not connect the VCL pin of an LSI with the internal step-down circuit to the Vcc power. A capacitor or capacitors for regulating the internal power voltage must be connected to the VCL pin. The Capacitor should be a laminated ceramic type (0.47 F x 1 or 0.47 F x 2 in parallel) and placed close to the pins.
Figure 20.26 Connection of VCL Capacitor
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Section 20 Electrical Characteristics
20.2
20.2.1
Electrical Characteristics of H8S/2134B
Absolute Maximum Ratings
Table 20.13 lists the absolute maximum ratings. Table 20.13 Absolute Maximum Ratings
Item Power supply voltage Power supply (VCL input)* Input voltage (other than ports 6 and 7) Input voltage (CIN input not selected for port 6) Input voltage (CIN input selected for port 6) Input voltage (port 7) Analog power supply voltage Analog input voltage Operating temperature Symbol VCC VCL Vin Vin Vin Vin AVCC VAN Topr Value -0.3 to +7.3 -0.3 to +4.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 V to lower of voltages VCC + 0.3 and AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 General specifications: -20 to +75 Wide temperature range specifications: -40 to +85 Operating temperature (flash memory programming/erasing) Topr General specifications: -20 to +75 Wide temperature range specifications: -40 to +85 Storage temperature Caution: Tstg -55 to +125 C Operating this LSI in excess of the absolute maximum ratings may result in permanent damage. Do not apply a voltage exceeding 7.0 V to input pins for the 5-V/4-V operation products. Power supply pin for the internal power supply. Do not apply a power to the VCL pin for the 5-V/4-V operation products. Connect a capacitor for regulating the internal power voltage between the VCL and GND pins. C Unit V V V V V V V V C
Note:
*
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Section 20 Electrical Characteristics
20.2.2
DC Characteristics
Table 20.14 lists the DC characteristics. Permissible output current values are shown in table 20.16. Table 20.14 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC*1 = 5.0 V 10%, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Schmitt P67 to P60 (1) trigger input (KWUL = voltage 00)*2*4, KIN7 to KIN0, 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 Schmitt P67 to P60 trigger input (KWUL = 01) voltage (level 4 switching)* P67 to P60 (KWUL = 10) Symbol VT- VT
+
Min. 1.0 --
Typ. Max. -- -- -- -- VCC x 0.7 --
Unit V
Test Conditions
VT - VT
+
-
0.4
VT- VT VT VT VT VT
+
VCC x 0.3 --
-
-- -- -- -- -- -- -- -- -- -- --
-- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 AVCC + 0.3 VCC + 0.3
V
VT - VT
- +
+
VCC x 0.05 VCC x 0.4 --
VT - VT P67 to P60 (KWUL = 11)
- +
+
-
VCC x 0.03 VCC x 0.45 -- 0.05 VCC x 0.7 VCC x 0.7 2.0 2.0
+ - VT - VT
Input high voltage
RES, STBY, (2) NMI, MD1, MD0 EXTAL Port 7 Input pins except (1) and (2) above
VIH
V
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Section 20 Electrical Characteristics
Item Input low voltage RES, STBY, MD1, MD0 (3)
Symbol VIL
Min. -0.3 -0.3
Typ. -- --
Max. 0.5 0.8
Unit V
Test Conditions
NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage VOH
VCC - 0.5 3.5
-- -- -- --
-- -- 0.4 1.0
V V V V
IOH = -200 A IOL = -1 mA IOL = 1.6 mA IOL = 10 mA
Output low voltage
All output pins Ports 1 to 3
VOL
-- --
Notes: 1. Do not leave the AVcc and AVss pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVcc pin to the power supply (VCC), or some other method. 2. Characteristics for P67 to P60 also indicate those for multiplexed signals of on-chip peripheral modules. 3. Characteristic for IRQ2 also indicate that for the multiplexed ADTRG signal. 4. The upper limit of the applicable voltage for port 6 is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is the applicable voltage.
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Section 20 Electrical Characteristics
Table 20.14 DC Characteristics (2) Conditions: VCC = 5.0 V 10%, AVCC*1 = 5.0 V 10%, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Tri-state leakage current (off state) Input pull-up MOS current Ports 1 to 6, 8, 9 ITSI Symbol Min. Iin -- -- -- -- Typ. -- -- -- -- Max. 10.0 1.0 1.0 1.0 A Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V
Ports 1 to 3 Port 6 (P6PUE = 1) Port 6 (P6PUE = 1)
-IP
30 60 15 -- -- --
-- -- -- -- -- -- 55 36 1.0 -- 1.2 0.01
300 600 200 80 50 15 70 55 5.0 20.0 2.0 5.0
A
Vin = 0 V
Input RES capacitance NMI
(4) Cin
pF
Input pins except (4) above Current consumption*2 Normal operation Sleep mode Standby mode*
3
Vin = 0 V, f = 1 MHz, Ta = 25C
ICC
-- -- -- --
mA mA A
f = 20 MHz f = 20 MHz Ta 50C 50C < Ta
Analog power supply current
During A/D, D/A conversion
AlCC
-- --
mA
Idle
A
AVCC = 2.0 V to 5.5 V
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Section 20 Electrical Characteristics
Item Reference power supply 4 current*
Symbol
Min. -- -- --
Typ. 0.5 2.0 0.01 -- -- --
Max. 1.0 5.0 5.0 5.5 5.5 --
Unit mA
Test Conditions
During A/D conversion Alref During A/D, D/A conversion Idle
1
A V Operating Idle/not used V
Analog power supply voltage*
AVCC
4.5 2.0
RAM standby voltage
VRAM
2.0
Notes: 1. Do not leave the AVCC and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVCC pin to the power supply (VCC), or some other method. 2. Current consumption values are for VIH min. = VCC - 0.2 V and VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs disabled. 3. The values are for VRAM VCC < 4.5 V, VIH min. = VCC- 0.2 V and VIL max. = 0.2 V. 4. The reference power supply current (Alref) is added to the analog power supply current (AlCC).
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Section 20 Electrical Characteristics
Table 20.14 DC Characteristics (3) Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Schmitt P67 to P60 (1) trigger input (KWUL = 24 voltage 00)* * , KIN7 to KIN0, 3 IRQ2 to IRQ0* , IRQ5 to IRQ3 Symbol VT- VT VT VT
+
Min. 1.0 --
Typ. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VCC x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.7 -- -- VCC x 0.8 -- -- VCC x 0.9 -- VCC + 0.3 VCC + 0.3 AVCC + 0.3 VCC + 0.3
Test Unit Conditions V VCC = 4.5 V to 5.5 V
VT - VT
- +
+
-
0.4 0.8 -- 0.3 VCC x 0.3 --
V
VCC = 4.0 V to 4.5 V
VT+ - VT- Schmitt P67 to P60 trigger input (KWUL = 01) voltage (level switching) P67 to P60 (KWUL = 10) VT- VT VT VT VT
+
V
VCC = 4.0 V to 5.5 V
VT - VT
- +
+
-
VCC x 0.05 VCC x 0.4 --
VT - VT P67 to P60 (KWUL = 11)
-
+
-
VCC x 0.03 VCC x 0.45 -- 0.05 VCC - 0.7 VCC x 0.7 2.0 2.0
VT+
+ - VT - VT
Input high voltage
RES, STBY, (2) NMI, MD1, MD0 EXTAL Port 7 Input pins except (1) and (2) above
VIH
V
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Section 20 Electrical Characteristics
Item Input low voltage RES, STBY, MD1, MD0 (3)
Symbol VIL
Min. -0.3 -0.3
Typ. -- --
Max. 0.5 0.8
Test Unit Conditions V
NMI, EXTAL, input pins except (1) and (3) above Output high All output pins voltage VOH
VCC - 0.5 3.5
-- --
-- --
V V
IOH = -200 A IOH = -1 mA, VCC = 4.5 V to 5.5 V IOH = -1 mA, VCC = 4.0 V to 4.5 V IOL = 1.6 mA IOL = 10 mA
3.0
--
--
V
Output low voltage
All output pins Ports 1 to 3
VOL
-- --
-- --
0.4 1.0
V V
Notes: 1. Do not leave the AVcc and AVss pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVCC pin to the power supply (VCC), or some other method. 2. Characteristics for P67 to P60 also indicate those for multiplexed signals of on-chip peripheral modules. 3. Characteristic for IRQ2 also indicate that for the multiplexed ADTRG signal. 4. The upper limit of the applicable voltage for port 6 is VCC + 0.3 V when CIN input is not selected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CIN input is selected. When a pin is in output mode, the output voltage is the applicable voltage.
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Section 20 Electrical Characteristics
Table 20.14 DC Characteristics (4) Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Input leakage current RES STBY, NMI, MD1, MD0 Port 7 Tri-state leakage current (off state) Input pull-up MOS current Ports 1 to 6, 8, 9 ITSI Symbol Iin Min. -- -- -- -- Typ. -- -- -- -- Max. 10.0 1.0 1.0 1.0 A Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V
Ports 1 to 3 Port 6 (P6PUE = 1) Port 6 (P6PUE = 1) Ports 1 to 3 Port 6 (P6PUE = 1) Port 6 (P6PUE = 1)
-IP
30 60 15 20 40 10
-- -- -- -- --
300 600 200 200 500 150
A
Vin = 0 V, VCC = 4.5 V to 5.5 V Vin = 0 V, VCC = 4.0 V to 4.5 V Vin = 0 V, f = 1 MHz, Ta = 25C
A
Input RES capacitance NMI
(4)
Cin
-- -- --
-- -- -- 45 30 1.0 --
80 50 15 58 46 5.0 20.0
pF
Input pins except (4) above Current consumption*2 Normal operation Sleep mode Standby mode*
3
ICC
-- -- -- --
mA mA A
f = 16 MHz f = 16 MHz Ta 50C 50C < Ta
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Section 20 Electrical Characteristics
Item Analog power supply current Reference power supply 4 current* During A/D, D/A conversion Idle
Symbol AlCC
Min. -- -- -- -- --
Typ. 1.2 0.01 0.5 2.0 0.01 -- -- --
Max. 2.0 5.0 1.0 5.0 5.0 5.5 5.5 --
Unit mA A mA
Test Conditions
AVCC = 2.0 V to 5.5 V
During A/D conversion Alref During A/D, D/A conversion Idle
1
A V Operating Idle/not used V
Analog power supply voltage*
AVCC VRAM
4.0 2.0
RAM standby voltage
2.0
Notes: 1. Do not leave the AVCC and AVSS pins open even if the A/D converter and D/A converter are not used. Even if the A/D converter and D/A converter are not used, apply a voltage in the range from 2.0 V to 5.5 V by connecting the AVCC pin to the power supply (VCC), or some other method. 2. Current consumption values are for VIH min. = VCC - 0.2 V and VIL max. = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs disabled. 3. The values are for VRAM VCC < 4.0 V, VIH min. = VCC- 0.2 V and VIL max. = 0.2 V. 4. The reference power supply current (Alref) is added to the analog power supply current (AlCC).
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Section 20 Electrical Characteristics
Table 20.15 Permissible Output Currents Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Permissible output low current (per pin) Permissible output low current (total) Ports 1 to 3 Other output pins Total of ports 1 to 3 Total of all output pins, including the above All output pins Total of all output pins -IOH -IOH IOL Symbol IOL Min. -- -- -- -- -- -- Typ. -- -- -- -- -- -- Max. 10 2 80 120 2 40 mA mA mA Unit mA
Permissible output high current (per pin) Permissible output high current (total)
Notes: 1. To ensure reliability, do not exceed the output current values in table 20.3. 2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 20.27 and 20.28.
This LSI
2 k Port
Darlington pair
Figure 20.27 Darlington Pair Driving Circuit (Example)
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Section 20 Electrical Characteristics
This LSI
600 Ports 1 to 3
LED
Figure 20.28 LED Driving Circuit (Example) 20.2.3 AC Characteristics
Figure 20.29 shows the test conditions for the AC characteristics.
VCC RL LSI output pin C = 30 pF: All output ports RL = 2.4 k RH = 12 k I/O timings are measured: * at 0.8 V for the low level * at 2.0 V for the high level
C
RH
Figure 20.29 Output Load Circuit
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Section 20 Electrical Characteristics
Clock Timing: Table 20.16 shows the clock timing. The clock timing specified here covers clock () output and oscillation stabilization times of the clock pulse generator (crystal) and external clock input (the EXTAL pin). For details on external clock input (the EXTAL pin and EXCL pin) timing, see section 17, Clock Pulse Generator. Table 20.16 Clock Timing Condition A: VCC = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rising time Clock falling time Symbol Min. tcyc tCH tCL tCr tCf 62.5 20 20 -- -- 10 8 500 Max. 500 -- -- 10 10 -- -- -- Condition A 20 MHz Min. 50 17 17 -- -- 10 8 500 Max. 500 -- -- 8 8 -- -- -- Unit ns ns ns ns ns ms ms s Figure 20.31 Figure 20.32 Reference Figure 20.30 Figure 20.30
Oscillation stabilization time at reset tOSC1 (crystal) Oscillation stabilization time at leaving software standby (crystal) External clock output stabilization delay time tOSC2 tDEXT
tcyc
tCH
tCf
tCL
tCr
Figure 20.30 System Clock Timing
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Section 20 Electrical Characteristics
EXTAL
tDEXT
tDEXT
VCC
STBY tOSC1 RES tOSC1
Figure 20.31 Oscillation Stabilization Timing
NMI
IRQi (i = 0, 1, 2, 6, 7)
tOSC2
Figure 20.32 Oscillation Stabilization Timing (Leaving Software Standby Mode)
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Section 20 Electrical Characteristics
Control Signal Timing: Table 20.17 shows the control signal timing. The only external interrupts that can be received during this LSI operating on the subclock ( = 32.768 kHz) are NMI, IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7. Table 20.17 Control Signal Timing Condition A: VCC = 5.0 V 10%, VSS = 0 V, = 32.768 kHz or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, = 32.768 kHz or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B Condition A 16 MHz Item RES setup time RES pulse width NMI setup time (NMI) NMI hold time (NMI) NMI pulse width (leaving software standby mode) IRQ setup time (IRQ7 to IRQ0) IRQ hold time(IRQ7 to IRQ0) IRQ pulse width (IRQ7, IRQ6, IRQ2 to IRQ0) (leaving software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- 20 MHz Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- Unit ns tcyc ns ns ns ns ns ns Figure 20.34 Test Conditions Figure 20.33
tRESS RES
tRESS
tRESW
Figure 20.33 Reset Input Timing
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Section 20 Electrical Characteristics
tNMIS
NMI tNMIW
tNMIH
IRQi (i = 7 to 0) tIRQS
tIRQW tIRQH
IRQi Edge input (i = 7 to 0)
tIRQS
IRQi Level input (i = 7 to 0)
Figure 20.34 Interrupt Input Timing Bus Timing: Table 20.18 shows the bus timing. Operation in external extended mode is not guaranteed when this LSI is operating on the subclock ( = 32.768 kHz).
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Section 20 Electrical Characteristics
Bus Timing: Table 20.18 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock ( = 32.768 kHz). Table 20.18 Bus Timing Condition A: VCC = 5.0 V 10%, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Address delay time Address setup time Address hold time CS delay time (IOS) AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time
Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5
Condition A 20 MHz Min. -- 0.5 x tcyc - 15 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- Max. 20 -- -- 20 30 30 30 -- -- 1.0 x tcyc - 30 1.5 x tcyc - 25 2.0 x tcyc - 30 2.5 x tcyc - 25 3.0 x tcyc - 30 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figures 20.35 to 20.39
Symbol Min. tAD tAS tAH tCSD tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- -- 20 0 -- -- -- -- --
Max. 30 -- -- 30 45 45 45 -- -- 1.0 x tcyc - 40 1.5 x tcyc - 35 2.0 x tcyc - 40 2.5 x tcyc - 35 3.0 x tcyc - 40
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Section 20 Electrical Characteristics
Condition B 16 MHz Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time Symbol Min. tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH -- -- 1.0 x tcyc - 30 1.5 x tcyc - 30 -- 0 15 45 5 Max. 45 45 -- -- 45 -- -- -- --
Condition A 20 MHz Min. -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0 10 30 5 Max. 30 30 -- -- 30 -- -- -- -- Test Unit Conditions ns ns ns ns ns ns ns ns ns Figures 20.35 to 20.39
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Section 20 Electrical Characteristics
T1
T2
tAD A15 to A0, IOS* tCSD AS* tAS tAH tASD tASD
tRSD1 RD (read) tAS
tACC2
tRSD2
tACC3 D7 to D0 (read)
tRDS
tRDH
tWRD2 WR (write) tAS tWDD D7 to D0 (write) tWSW1
tWRD2 tAH tWDH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.35 Basic Bus Timing (Two-State Access)
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Section 20 Electrical Characteristics
T1
T2
T3
tAD
A15 to A0, IOS*
tCSD
tAS
tASD
tASD
tAH
AS*
tRSD1 RD (read)
tAS
tACC4
tRSD2
tACC5 D7 to D0 (read)
tRDS
tRDH
tWRD1 WR (write)
tWDD tWDS
tWRD2
tAH
tWSW2
tWDH
D7 to D0 (write)
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.36 Basic Bus Timing (Three-State Access)
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Section 20 Electrical Characteristics
T1
T2
TW
T3
A15 to A0, IOS*
AS*
RD (read) D7 to D0 (read) WR (write)
D7 to D0 (write)
tWTS tWTH
WAIT tWTS tWTH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.37 Basic Bus Timing (Three-State Access with One Wait Cycle)
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Section 20 Electrical Characteristics
T1
T2 or T3
T1
T2
tAD
A15 to A0, IOS*
tAS
tASD tASD
tAH
AS*
tRSD2
RD (read)
tACC3 D7 to D0 (read)
tRDS
tRDH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.38 Burst ROM Access Timing (Two-State Access)
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Section 20 Electrical Characteristics
T1
T2 or T3
T1
tAD
A15 to A0, IOS*
AS*
tRSD2
RD (read)
tACC1 D7 to D0 (read)
tRDS
tRDH
Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.
Figure 20.39 Burst ROM Access Timing (One-State Access)
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Section 20 Electrical Characteristics
Timing of On-Chip Peripheral Modules: Tables 20.19 shows the on-chip peripheral module timing. The only on-chip peripheral modules that can operate during this LSI operating on the subclock ( = 32.768 kHz) are the I/O ports, external interrupts (NMI, IRQ0, IRQ1, IRQ2, IRQ6, and IRQ7), watchdog timer, and the 8-bit timer (channels 0 and 1). Table 20.19 Timing of On-Chip Peripheral Modules Condition A: VCC = 5.0 V 10%, VSS = 0 V, = 32.768 kHz* or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, = 32.768 kHz* or 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Note: * For modules that can operate during this LSI operating on the subclock
Condition B 16 MHz Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Both edges Condition A 20 MHz Test Conditions Figure 20.40
Symbol Min. Max. Min. Max. Unit tPWD tPRS tPRH tFTOD tFTIS tFTCS -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 -- 50 -- -- 50 -- -- -- -- 50 -- -- -- -- 50 -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 -- 50 -- -- 50 -- -- -- -- 50 -- -- -- -- 50 ns tcyc ns tcyc ns ns
Figure 20.41 Figure 20.42
Single edge tFTCWH tFTCWL tTMOD tTMRS tTMCS
Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Both edges
Figure 20.43 Figure 20.45 Figure 20.44
Single edge tTMCWH tTMCWL tPWOD
PWMX
Pulse output delay time
Figure 20.46
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Section 20 Electrical Characteristics
Condition B 16 MHz Item SCI Input clock cycle
Condition A 20 MHz Test Conditions Figure 20.47
Symbol Min. Max. Min. Max. Unit Asynchronous tScyc Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS 4 6 0.4 -- -- -- 50 50 30 -- -- 0.6 1.5 1.5 50 -- -- -- 4 6 0.4 -- -- -- 50 50 30 -- -- 0.6 1.5 1.5 50 -- -- -- ns ns tScyc tcyc tcyc
Input clock pulse width Input clock rising time Input clock falling time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter Note: *
Figure 20.48
Figure 20.49
Only on-chip peripheral modules that can be used in subclock operation
T1
T2
tPRS tPRH
Ports 1 to 9 (read)
tPWD
Ports 1 to 6, 8, 9 (write)
Figure 20.40 I/O Port Input/Output Timing
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Section 20 Electrical Characteristics
tFTOD FTOA, FTOB tFTIS
FTIA, FTIB, FTIC, FTID
Figure 20.41 FRT Input/Output Timing
tFTCS FTCI tFTCWL tFTCWH
Figure 20.42 FRT Clock Input Timing
tTMOD
TMO0, TMO1
Figure 20.43 8-Bit Timer Output Timing
Rev. 1.00 Jun.24, 2005 Page 490 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
tTMCS
tTMCS
TMCI0, TMCI1, TMIY
tTMCWL tTMCWH
Figure 20.44 8-Bit Timer Clock Input Timing
tTMRS
TMRI0, TMRI1, TMIY
Figure 20.45 8-Bit Timer Reset Input Timing
tPWOD
PWX1, PWX0
Figure 20.46 PWMX Output Timing
tSCKW tSCKr tSCKf
SCK0 to SCK2
tScyc
Figure 20.47 SCK Clock Input Timing
Rev. 1.00 Jun.24, 2005 Page 491 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
SCK0 to SCK2
tTXD
TxD0 to TxD2 (transmit data)
tRXS
tRXH
RxD0 to RxD2 (receive data)
Figure 20.48 SCI Input/Output Timing (Synchronous Mode)
tTRGS ADTRG
Figure 20.49 A/D Converter External Trigger Input Timing
Testing voltage: 0.4Vcc 50 pF
Figure 20.50 Tester Measurement Condition
Rev. 1.00 Jun.24, 2005 Page 492 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
20.2.4
A/D Conversion Characteristics
Tables 20.20 and 20.21 list the A/D conversion characteristics. Table 20.20 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Resolution Conversion time*3 Analog input capacitance -- -- -- -- -- Min. Typ. 10 8.4 20 10* 5* Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy -- -- -- -- -- -- -- -- -- --
2 1
Condition A 20 MHz
Max.
Min.
Typ. 10
Max.
Unit bits
-- -- --
-- -- --
6.7 20 10* 5*
2 1
s pF k
Permissible signal-source impedance --
3.0 3.5 3.5 0.5 4.0
-- -- -- -- --
-- -- -- -- --
3.0 3.5 3.5 0.5 4.0
LSB LSB LSB LSB LSB
Notes: 1. When conversion time 11.17 s ( 12 MHz with CKS = 1 or CKS = 0) 2. When conversion time < 11.17 s ( > 12 MHz with CKS = 1) 3. When this LSI operates on the maximum operating frequency in single-chip mode
Rev. 1.00 Jun.24, 2005 Page 493 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Table 20.21 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Resolution Conversion time*
3
Condition A 20 MHz
Min.
Typ. 10
Max.
Min.
Typ. 10
Max.
Unit bits
-- --
-- -- --
8.4 20 10* 5*
2 1
-- -- --
-- -- --
6.7 20 10* 5*
2 1
s pF k
Analog input capacitance
Permissible signal-source impedance --
Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy
-- -- -- -- --
-- -- -- -- --
5.0 5.5 5.5 0.5 6.0
-- -- -- -- --
-- -- -- -- --
5.0 5.5 5.5 0.5 6.0
LSB LSB LSB LSB LSB
Notes: 1. When conversion time 11.17 s ( 12 MHz with CKS = 1 or CKS = 0) 2. When conversion time < 11.17 s ( > 12 MHz with CKS = 1) 3. When this LSI operates on the maximum operating frequency in single-chip mode
Rev. 1.00 Jun.24, 2005 Page 494 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
20.2.5
D/A Conversion Characteristics
Table 20.22 lists the D/A conversion characteristics. Table 20.22 D/A Conversion Characteristics Condition A: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications) Condition B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to maximum operating frequency, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Condition B 16 MHz Item Resolution Conversion time Absolute accuracy With 20 pF load capacitance -- With 2 M load resistance With 4 M load resistance -- -- Condition A 20 MHz
Min. Typ. Max. Min. Typ. Max. Unit 8 -- 10 -- 8 -- 10 bits s
1.0 1.5 -- -- 1.0 --
1.0 1.5 LSB -- 1.0
Rev. 1.00 Jun.24, 2005 Page 495 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
20.2.6
Flash Memory Characteristics
Table 20.23 shows the flash memory characteristics. Table 20.23 Flash Memory Characteristics (Programming/Erasure) Conditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = -20 to +75C (General specifications), Ta = -40 to +85C (Wide temperature range specifications)
Item Programming time*1*2*4 Symbol Min. tP -- Typ. 10 Max. 200 Unit ms/ 128 bytes ms/ block times s s s s s s s s s s s times 1n6 7n 1000 Additional write Test Condition
Erasure time*1*3*6 Reprogramming count Programming Wait time after setting SWE bit*1 Wait time after setting PSU bit*1 Wait time after setting P bit*1*4
tE NWEC x y z1 z2 z3
-- -- 1 50 28 198 8 5 5 4 2 2 100 --
100 -- -- -- 30 200 10 -- -- -- -- -- -- --
1200 100 -- -- 32 202 12 -- -- -- -- -- -- 1000
Wait time after clearing P bit *1 Wait time after 1 clearing PSU bit * Wait time after setting PV bit *1 Wait time after dummy write*1 Wait time after 1 clearing PV bit * Wait time after clearing SWE bit *1 Maximum programming 145 count* * *
N
Rev. 1.00 Jun.24, 2005 Page 496 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
Item Erasure Wait time after setting SWE bit*1 Wait time after 1 setting ESU bit* Wait time after 16 setting E bit* * Wait time after 1 clearing E bit* Wait time after 1 clearing ESU bit* Wait time after 1 setting EV bit* Wait time after dummy-writing 1 H'FF* Wait time after 1 clearing EV bit* Wait time after 1 clearing SWE bit* Maximum erasure 167 count* * *
Symbol Min. x y z 1 100 10 10 10 20 2
Typ. -- -- -- -- -- -- --
Max. -- -- 100 -- -- -- --
Unit s s ms s s s s
Test Conditions
N
4 100 --
-- -- --
-- -- 120
s s times
Notes: 1. Set the times according to the programming/erasing algorithms. 2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It does not include the programming-verifying time.) 3. Block erasing time (Shows the total period for which the E bit in FLMCR1 is set. It does not include the erasing-verifying time.) 4. Maximum programming time (tP (max.)) tP (max.) = (wait time after setting P bit (z1) + (z3)) x 6 + wait time after setting P bit (z2) x ((N) - 6) 5. The maximum programming court (N) should be set according to the actual set value of z1, z2 and z3 to allow programming within the maximum programming time (tP (max.)). The wait time after setting the P bit (z1, z2, and z3) should be alternated according to the programming count (n) as follows: 1n6 z1 = 30s, z3 = 10s 7 n 1000 z2 = 200s 6. Maximum erasure time (tE (max.)) tE (max.) = Wait time after setting E bit (z) x maximum erasure count (N) 7. The maximum erasure count (N) should be set according to the actual set value of z to allow erasing within the maximum erasure time (tE (max.)).
Rev. 1.00 Jun.24, 2005 Page 497 of 510 REJ09B0241-0100
Section 20 Electrical Characteristics
20.2.7
Usage Note
* LSI with Internal Step-Down Circuit This LSI includes an internal step-down circuit which automatically step down the internal power voltage to an appropriate level. A capacitor or capacitors for regulating the internal power voltage (one 0.47-F capacitor or two 0.47-F capacitors in parallel) must be placed between the internal step-down and VSS pins. For connection of the capacitor, see figure 20.51.
External capacitor for regulating internal power voltage
VCL
0.47 F x 1 or 0.47 F x 2 in parallel
LSI with internal step-down circuit
VSS
Do not connect the VCL pin of an LSI with the internal step-down circuit to the Vcc power. A capacitor or capacitors for regulating the internal power voltage must be connected to the VCL pin. The Capacitor should be a laminated ceramic type (0.47 F x 1 or 0.47 F x 2 in parallel) and placed close to the pins.
Figure 20.51 Connection of VCL Capacitor
Rev. 1.00 Jun.24, 2005 Page 498 of 510 REJ09B0241-0100
Appendix
Appendix A I/O Port States in Each Processing State
Table A.1
Port Name Pin Name Port 1 A7 to A0
I/O Port States in Each Processing State
MCU Operating Mode 1 2, 3 (EXPE = 1) Hardware Software Standby Standby Reset Mode Mode L T T kept*1 Watch Sleep Mode Mode kept*1 kept*1 Subsleep Mode kept*1 Subactive Mode A7 to A0 Address output/ input port I/O port L T T kept*
1
Program Execution State A7 to A0 Address output/ input port I/O port A15 to A8 Address output/ input port I/O port D15 to D8*3
2, 3 (EXPE = 0) Port 2 A15 to A8 1 2, 3 (EXPE = 1) kept*
1
kept*
1
kept*
1
A15 to A8 Address output/ input port I/O port
2, 3 (EXPE = 0) Port 3 D15 to D8*3 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 4 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 5 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 6 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 7 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 8 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 97 WAIT 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) kept kept kept kept T T T/kept T/kept T/kept T/kept T T kept kept kept kept T T T T T T T T kept kept kept kept T T kept kept kept kept T T kept kept kept kept kept kept kept kept T T T T T T
D15 to D8*3
I/O port I/O port
I/O port I/O port
I/O port
I/O port
I/O port
I/O port
Input port
Input port
I/O port
I/O port
WAIT/ I/O port I/O port
WAIT/ I/O port I/O port
Rev. 1.00 Jun.24, 2005 Page 499 of 510 REJ09B0241-0100
Appendix
MCU Operating Mode 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Ports 95 to 93 1 AS, HWR*4, 2, 3 (EXPE = 1) RD 2, 3 (EXPE = 0) Ports 92 to 91 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port 90 LWR*2 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port A*2 A23 to A16 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) Port B*2 D7 to D0 1 2, 3 (EXPE = 1) 2, 3 (EXPE = 0) kept kept kept kept T T T/kept T/kept T/kept T/kept T T kept kept*1 kept kept*1 kept kept*1 kept kept*1 T T H/kept H/kept H/kept H/kept LWR/ I/O port I/O port I/O port A23 to A16/ I/O port I/O port D7 to D0/ I/O port I/O port LWR/ I/O port I/O port I/O port A23 to A16/ I/O port I/O port D7 to D0/ I/O port I/O port H T kept T T kept kept kept kept kept kept kept T H H Hardware Software Standby Standby Reset Mode Mode
Clock output
Port Name Pin Name Port 96 EXCL
Watch Sleep Mode Mode [DDR = 1] clock output [DDR = 0] T H
Subsleep Mode EXCL input
Subactive Mode EXCL input
Program Execution State Clock output/ EXCL input/ input port
T
[DDR = 1] H EXCL input [DDR = 0] T
T
H
AS, HWR*4, RD I/O port I/O port
AS, HWR*4, RD I/O port I/O port
[Legend] H: High L: Low T: High-impedance state kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up MOSs remain on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR used. DDR: Data direction register Notes: 1. When the address output is selected, the previous address accessed is retained. 2. This signal is for the H8S/2144B and is not available for the H8S/2134B. 3. These signal names are for the H8S/2144B. D7 to D0 are used for the H8S/2134B. 4. This signal name is for the H8S/2144B. WR is used for the H8S/2134B.
Rev. 1.00 Jun.24, 2005 Page 500 of 510 REJ09B0241-0100
Appendix
Appendix B Product Codes
Product Type H8S/2144B Flash memory version Product Code HD64F2144B Mark Code F2144BFA20 F2144BTE20 H8S/2134B Flash memory version HD64F2134B F2134BFA20 F2134BTE20 Package (Code) 100-pin QFP (FP-100B) 100-pin TQFP (TFP-100B) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80B)
Note:
*
Some products above are in the developing or planning stage. Please contact Renesas agency to conform the present status of each product.
Rev. 1.00 Jun.24, 2005 Page 501 of 510 REJ09B0241-0100
Appendix
Appendix C Package Dimensions
16.0 0.3
14
Unit: mm
75 76
16.0 0.3
51 50
0.5
100
26
3.05 Max
2.70
0.08 M 1.0
*0.17 0.05 0.15 0.04
1 *0.22 0.05 0.20 0.04
25
1.0
0 - 8
0.12 +0.13 -0.12
0.10
0.5 0.2
Package Code
*Dimension including the plating thickness Base material dimension
JEDEC EIAJ Weight (reference value)
FP-100B -- Conforms 1.2 g
Figure C.1 Package Dimensions (FP-100B)
Rev. 1.00 Jun.24, 2005 Page 502 of 510 REJ09B0241-0100
Appendix
Unit: mm
16.0 0.2
14
75 76
16.0 0.2
51 50
100 1 *0.22 0.05 0.20 0.04 25
26
*0.17 0.05 0.15 0.04 1.20 Max
0.08 M
1.00
0.5
1.0
1.0
0 - 8
0.10
0.10 0.10
0.5 0.1
Package Code
*Dimension including the plating thickness Base material dimension
JEDEC JEITA Mass (reference value)
TFP-100B -- Conforms 0.5 g
Figure C.2 Package Dimensions (TFP-100B)
Rev. 1.00 Jun.24, 2005 Page 503 of 510 REJ09B0241-0100
Appendix
17.2 0.3
14
Unit: mm
41 40
0.65
60
61
17.2 0.3
80 1
*0.32 0.08
21 20
*0.17 0.05
0.15 0.04
0.30 0.06
0.12 M
2.70
3.05 Max
0.83
1.6
0.10 +0.15 -0.10
0 - 8
0.8 0.3
Package Code JEDEC JEITA Mass (reference value) FP-80A -- Conforms 1.2 g
0.10
*Dimension including the plating thickness Base material dimension
Figure C.3 Package Dimensions (FP-80A)
Rev. 1.00 Jun.24, 2005 Page 504 of 510 REJ09B0241-0100
Appendix
14.0 0.2
Unit: mm
41
40
12
60 61
14.0 0.2
80 1
*0.22 0.05
21 20
*0.17 0.05
0.5
1.00
0.20 0.04
0.10 M
1.25
0.15 0.04
1.20 Max
1.0
0 - 8 0.5 0.1
Package Code JEDEC JEITA Mass (reference value) TFP-80C -- Conforms 0.4 g
0.10
*Dimension including the plating thickness Base material dimension
Figure C.4 Package Dimensions (TFP-80C)
0.10 0.10
Rev. 1.00 Jun.24, 2005 Page 505 of 510 REJ09B0241-0100
Appendix
Rev. 1.00 Jun.24, 2005 Page 506 of 510 REJ09B0241-0100
Index
Numerics
14-Bit PWM Timer (PWMX)................. 183 16-Bit Count Mode................................. 246 16-Bit Free-Running Timer (FRT) ......... 197 8-Bit Timer (TMR) ................................. 227 CMIA ...................................................... 248 CMIAY ................................................... 248 CMIB ...................................................... 248 CMIBY ................................................... 248 Compare-Match Count Mode ................. 247 Condition field .......................................... 46 Condition-Code Register (CCR) ............... 29 Conversion Time..................................... 345 Crystal Resonator.................................... 382
A
A/D Converter ........................................ 335 ADI ......................................................... 347 Absolute Address...................................... 49 Address Map............................................. 67 Address Space........................................... 26 Addressing Modes .................................... 47 Analog Input Channel............................. 338 Arithmetic Operations Instructions........... 38 Asynchronous Mode............................... 290
D
D/A Converter......................................... 329 Data Transfer Instructions......................... 37 Direct Transitions.................................... 405
E B
Bcc............................................................ 44 Bit Manipulation Instructions ............. 42, 56 Bit rate .................................................... 282 Block Data Transfer Instructions.............. 46 Boot Mode .............................................. 366 Branch Instructions................................... 44 Break....................................................... 322 Buffered Input Capture Input.................. 212 Burst ROM Interface .............................. 129 EEPMOV Instruction................................ 58 Effective Address...................................... 52 Effective address extension....................... 46 Erasing/Erasing-Verifying ...................... 374 ERI.......................................................... 321 Error Protection....................................... 376 Exception Handling .................................. 69 Exception Vector Table ............................ 70 Extended Control Register (EXR) ............ 29 External Trigger ...................................... 346
F C
Cascaded Connection.............................. 246 Clear Timing........................................... 211 Clock Pulse Generator ............................ 381 Clock Synchronous Mode....................... 308 CMI......................................................... 248 Flash memory ......................................... 355 FOV ........................................................ 219 Framing error .......................................... 297
Rev. 1.00 Jun.24, 2005 Page 507 of 510 REJ09B0241-0100
G
General Registers...................................... 28
N
NMI interrupt.................................... 87, 267
H
Hardware Protection ............................... 376 Hardware Standby Mode ........................ 401
O
OCI ......................................................... 219 On-Board Programming Modes.............. 366 Operation field .......................................... 46 Output Compare Output.......................... 210 Overrun error .......................................... 297 OVI ......................................................... 248 OVIY ...................................................... 248
I
ICI........................................................... 219 Idle Cycle ............................................... 131 Immediate ................................................. 50 Increment Timing ................................... 209 Input Capture Input................................. 211 Instruction Set........................................... 35 Interrupt Control Modes ........................... 92 Interrupt Controller................................... 77 Interrupt Exception Handling ................... 73 Interrupt Exception Handling Vector Table ............................................. 89 Interrupt Mask Bit .................................... 30 Interval Timer Mode............................... 266 IrDA Operation....................................... 318
P
Parity error .............................................. 297 Power-Down Modes ............................... 389 Program Counter (PC) .............................. 29 Program-Counter Relative ........................ 50 Programmer Mode .................................. 378 Programming/Eraseing Protection .......... 376 Programming/Programming-Verifying... 371 Pulse Output............................................ 209
L
Logic Operations Instructions................... 40
R
Register Direct .......................................... 48 Register field............................................. 46 Register Indirect........................................ 48 Register Indirect with Displacement......... 48 Register Indirect with Post-Increment ...... 48 Register Indirect with Pre-Decrement....... 49 Registers ABRKCR .......... 81, 408, 414, 419, 424 ADCR ............. 341, 412, 418, 423, 428 ADCSR ........... 339, 412, 418, 423, 428 ADDR ............. 338, 412, 418, 423, 428 BAR .................. 81, 408, 414, 419, 424 BCR ................ 109, 411, 417, 422, 427 BRR ................ 282, 412, 417, 422, 428
M
Mark State .............................................. 322 MCU Operating Mode Selection .............. 59 Medium-Speed Mode ............................. 397 Memory Indirect....................................... 50 Module Stop Mode ................................. 405 Multiprocessor Communication Function.................................................. 301
Rev. 1.00 Jun.24, 2005 Page 508 of 510 REJ09B0241-0100
DACNT ...........184, 410, 416, 421, 426 DACR .....188, 331, 410, 413, 416, 418, 420, 423, 426, 429 DADR0............330, 413, 418, 423, 429 DADR1............330, 413, 418, 423, 429 EBR1 ...............364, 408, 414, 419, 424 EBR2 ...............364, 408, 414, 419, 424 FLMCR1..........362, 408, 414, 419, 424 FLMCR2..........363, 408, 414, 419, 424 FRC .................200, 409, 415, 420, 425 ICR ..........80, 200, 408, 409, 414, 415, 419, 420, 424, 425 IER ...................83, 411, 417, 422, 427 ISCR ..................82, 408, 414, 419, 424 ISR ...................84, 408, 414, 419, 424 KBCOMP ........342, 408, 414, 419, 424 KMIMR .............85, 413, 418, 423, 429 KMIMRA ..........85, 413, 418, 423, 429 KMPCR ...157, 158, 413, 418, 423, 429 LPWRCR.........392, 408, 414, 419, 424 MDCR ...............60, 411, 417, 422, 427 MSTPCR .........393, 408, 414, 419, 424 OCR.................200, 409, 415, 420, 425 OCRDM.......................................... 201 P1DDR.............140, 410, 416, 421, 427 P1DR ...............141, 410, 416, 421, 427 P1PCR .............141, 410, 416, 421, 426 P2DDR.............143, 410, 416, 421, 427 P2DR ...............144, 410, 416, 421, 427 P2PCR .............144, 410, 416, 421, 426 P3DDR.............147, 410, 416, 421, 427 P3DR ...............147, 411, 416, 421, 427 P3PCR .............148, 410, 416, 421, 426 P4DDR.............150, 410, 416, 421, 427 P4DR ...............150, 411, 416, 421, 427 P5DDR.............154, 411, 417, 421, 427 P5DR .......154, 157, 411, 417, 421, 427 P6DDR.............156, 411, 417, 421, 427 P6DR ...................... 411, 417, 422, 427 P7PIN...............162, 411, 417, 422, 427
P8DDR............ 164, 411, 417, 422, 427 P8DR............... 165, 411, 417, 422, 427 P9DDR............ 168, 411, 417, 422, 427 P9DR............... 169, 411, 417, 422, 427 PADDR........... 172, 410, 416, 421, 426 PAODR........... 173, 410, 416, 421, 426 PAPIN............. 173, 410, 416, 421, 426 PBDDR ........... 179, 411, 417, 422, 427 PBODR ........... 180, 411, 417, 422, 427 PBPIN ............. 180, 411, 417, 422, 427 RDR ................ 274, 412, 418, 423, 428 RSR ................................................ 274 SBYCR ........... 390, 408, 414, 419, 424 SCMR ............. 281, 412, 418, 423, 428 SCR ................ 277, 412, 418, 423, 428 SMR ................ 275, 412, 417, 422, 428 SSR ................ 279, 412, 418, 423, 428 STCR ................ 63, 411, 417, 422, 427 SYSCR.............. 61, 411, 417, 422, 427 SYSCR2.................. 408, 414, 419, 424 TCNT ............. 231, 259, 410, 412, 416, 417, 421, 422, 426, 428 TCOR.............. 231, 411, 417, 422, 428 TCR ....... 206, 232, 409, 411, 415, 417, 420, 422, 425, 427 TCSR ..... 203, 235, 260, 409, 410, 411, 415, 416, 417, 420, 421, 422, 425, 426, 427 TDR ........................ 412, 418, 423, 428 TIER................ 202, 409, 415, 420, 425 TISR........................ 240, 413, 418, 423 TOCR.............. 207, 409, 415, 420, 425 TSR ................................................ 274 WSCR ............. 110, 411, 417, 422, 427 Reset ......................................................... 71 Reset Exception Handling......................... 71 RXI ......................................................... 321
Rev. 1.00 Jun.24, 2005 Page 509 of 510 REJ09B0241-0100
S
Serial Communication Interface (SCI and IrDA) ....................................... 271 Shift Instructions ...................................... 41 Single Mode............................................ 343 Sleep Mode............................................. 398 Software Protection ................................ 376 Software Standby Mode ......................... 399 Stack pointer (SP)..................................... 28 Stack Status .............................................. 74 Subactive Mode ...................................... 404 Subsleep Mode ....................................... 403 System Control Instructions ..................... 45
TDR ........................................................ 274 TEI .......................................................... 321 Toggle output.......................................... 252 Trap Instruction Exception Handling........ 73 TXI.......................................................... 321
U
User Program Mode................................ 370
W
Wait Control ........................................... 127 Watch Mode............................................ 402 Watchdog Timer (WDT)......................... 257 Watchdog Timer Mode ........................... 264 WOVI ..................................................... 267
T
TCNT Count Timing .............................. 242
Rev. 1.00 Jun.24, 2005 Page 510 of 510 REJ09B0241-0100
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2144B, H8S/2134B
Publication Date: Rev.1.00, Jun. 24, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.
2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
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